This is a major re-design of the way code is scheduled in Verilator,
with the goal of properly supporting the Active and NBA regions of the
SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4.
With this change, all internally generated clocks should simulate
correctly, and there should be no more need for the `clock_enable` and
`clocker` attributes for correctness in the absence of Verilator
generated library models (`--lib-create`).
Details of the new scheduling model and algorithm are provided in
docs/internals.rst.
Implements #3278
* Add detailed location to XML output
* Fixing build failures
* less cryptic regulary expressions
* correcting typo in test
* Adding file letter to the location attribute, and cleaning up the regular expression in the tests.
* Add remaining test expected output files for XML changes
* spacing fix, adding documentation on changes
* Add more directives to configuration files
Allow to set the same directives in configuration files that can also
be set by comment attributes (such as /* verilator public */ etc).
* Add support for lint messsage waivers
Add configuration file switch '-match' for lint_off. It takes a string
with wildcards allowed and warnings will be matched against it (if
rule and file also match). If it matches, the warning is waived.
Fixes#1649 and #1514Closes#2072
Experimental and disabled unless -OD or -O3 used (for now),
Please try it as may get some significant speedups.
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
