github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-03 21:27:35 +00:00
Code Issues Packages Projects Releases Wiki Activity

Tests: Check need -cc message

Browse Source
This commit is contained in:
Wilson Snyder 2020-05-16 07:10:44 -04:00
parent f77058774e
commit ffd461dcf8
3 changed files with 40 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
test_regress/t/t_flag_noop_bad.out Normal file
View File

@ -0,0 +1 @@
%Error: verilator: Need --cc, --sc, --cdc, --dpi-hdr-only, --lint-only, --xml-only or --E option

22
test_regress/t/t_flag_noop_bad.pl Executable file
View File

@ -0,0 +1,22 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
run(cmd => ["../bin/verilator",
"t_flag_noop_bad.v"],
fails => 1,
logfile => "$Self->{obj_dir}/sim.log",
expect_filename => $Self->{golden_filename},
verilator_run => 1,
);
ok(1);
1;

17
test_regress/t/t_flag_noop_bad.v Normal file
View File

@ -0,0 +1,17 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
int u1;
int u1;
int u1;
int u1;
int u1;
int u1;
int u1;
endmodule