diff --git a/Changes b/Changes
index 0036913df..bb2901461 100644
--- a/Changes
+++ b/Changes
@@ -11,6 +11,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***   Support tri0 and tri1, bug462.  [Alex Solomatnikov]
 
+***   Support nmos and pmos, bug488.  [Alex Solomatnikov]
+
 ***   Fix generate operators not short circuiting, bug413.  [by Jeremy Bennett]
 
 
diff --git a/bin/verilator b/bin/verilator
index 9ac97cc2f..7a09db46c 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -2239,8 +2239,8 @@ practice, just setting all variables to one at startup finds most problems.
 =head2 Tri/Inout
 
 Verilator converts some simple tristate structures into two state.  Pullup,
-pulldown, bufif0, bufif1, notif0, notif1, tri0 and tri1 are also supported.
-Simple comparisons with === 1'bz are also supported.
+pulldown, bufif0, bufif1, notif0, notif1, pmos, nmos, tri0 and tri1 are
+also supported.  Simple comparisons with === 1'bz are also supported.
 
 An assignment of the form:
 
diff --git a/src/verilog.y b/src/verilog.y
index fe4478d18..182e4cbc8 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -2705,10 +2705,10 @@ gateDecl<nodep>:
 	|	yXNOR delayE gateXnorList ';'		{ $$ = $3; }
 	|	yPULLUP delayE gatePullupList ';'	{ $$ = $3; }
 	|	yPULLDOWN delayE gatePulldownList ';'	{ $$ = $3; }
+	|	yNMOS delayE gateBufif1List ';'		{ $$ = $3; }  // ~=bufif1, as don't have strengths yet
+	|	yPMOS delayE gateBufif0List ';'		{ $$ = $3; }  // ~=bufif0, as don't have strengths yet
 	//
 	|	yTRAN delayE gateUnsupList ';'		{ $$ = $3; GATEUNSUP($3,"tran"); } // Unsupported
-	|	yNMOS delayE gateUnsupList ';'		{ $$ = $3; GATEUNSUP($3,"nmos"); } // Unsupported
-	|	yPMOS delayE gateUnsupList ';'		{ $$ = $3; GATEUNSUP($3,"pmos"); } // Unsupported
 	|	yRCMOS delayE gateUnsupList ';'		{ $$ = $3; GATEUNSUP($3,"rcmos"); } // Unsupported
 	|	yCMOS delayE gateUnsupList ';'		{ $$ = $3; GATEUNSUP($3,"cmos"); } // Unsupported
 	|	yRNMOS delayE gateUnsupList ';'		{ $$ = $3; GATEUNSUP($3,"rmos"); } // Unsupported
diff --git a/test_regress/t/t_tri_gate.cpp b/test_regress/t/t_tri_gate.cpp
index ed97541bc..b52fc202b 100644
--- a/test_regress/t/t_tri_gate.cpp
+++ b/test_regress/t/t_tri_gate.cpp
@@ -13,6 +13,10 @@
 # include "Vt_tri_gate_notif0.h"
 #elif defined(T_NOTIF1)
 # include "Vt_tri_gate_notif1.h"
+#elif defined(T_PMOS)
+# include "Vt_tri_gate_pmos.h"
+#elif defined(T_NMOS)
+# include "Vt_tri_gate_nmos.h"
 #else
 # error "Unknown test"
 #endif
diff --git a/test_regress/t/t_tri_gate.v b/test_regress/t/t_tri_gate.v
index 01364fadf..7209f354f 100644
--- a/test_regress/t/t_tri_gate.v
+++ b/test_regress/t/t_tri_gate.v
@@ -26,6 +26,10 @@ module tbuf (input A, input OE, output Z);
    notif0 (Z, !A, !OE);
 `elsif T_NOTIF1
    notif1 (Z, !A, OE);
+`elsif T_PMOS
+   pmos (Z, A, !OE);
+`elsif T_NMOS
+   nmos (Z, A, OE);
 `elsif T_COND
    assign Z = (OE) ? A : 1'bz;
 `else
diff --git a/test_regress/t/t_tri_gate_nmos.pl b/test_regress/t/t_tri_gate_nmos.pl
new file mode 100755
index 000000000..ea2b89c32
--- /dev/null
+++ b/test_regress/t/t_tri_gate_nmos.pl
@@ -0,0 +1,27 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_tri_gate.v");
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+compile (
+	 make_top_shell => 0,
+	 make_main => 0,
+	 v_flags2 => ['+define+T_NMOS',],
+	 make_flags => 'CPPFLAGS_ADD=-DT_NMOS',
+	 verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"],
+    );
+
+execute (
+	 check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_tri_gate_pmos.pl b/test_regress/t/t_tri_gate_pmos.pl
new file mode 100755
index 000000000..f61945fae
--- /dev/null
+++ b/test_regress/t/t_tri_gate_pmos.pl
@@ -0,0 +1,27 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_tri_gate.v");
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+compile (
+	 make_top_shell => 0,
+	 make_main => 0,
+	 v_flags2 => ['+define+T_PMOS',],
+	 make_flags => 'CPPFLAGS_ADD=-DT_PMOS',
+	 verilator_flags2 => ["--exe $Self->{t_dir}/t_tri_gate.cpp"],
+    );
+
+execute (
+	 check_finished=>1,
+    );
+
+ok(1);
+1;