diff --git a/src/verilog.y b/src/verilog.y
index 5a778c838..96ce8a826 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -917,8 +917,14 @@ package_import_itemList<nodep>:
 
 package_import_item<nodep>:	// ==IEEE: package_import_item
 		idAny/*package_identifier*/ yP_COLONCOLON package_import_itemObj
-			{ $$ = new AstPackageImport($<fl>2, VN_CAST($<scp>1, Package), *$3);
-			  SYMP->importItem($<scp>1,*$3); }
+			{
+			  if (!VN_CAST($<scp>1, Package)) {
+			      $$ = NULL;
+			      $<fl>1->v3error("Importing from missing package '" << *$<strp>1 << "'");
+			  } else {
+			      $$ = new AstPackageImport($<fl>2, VN_CAST($<scp>1, Package), *$3);
+			      SYMP->importItem($<scp>1,*$3);
+			  } }
 	;
 
 package_import_itemObj<strp>:	// IEEE: part of package_import_item
diff --git a/test_regress/t/t_lint_import_name2_bad.out b/test_regress/t/t_lint_import_name2_bad.out
new file mode 100644
index 000000000..b95efdba7
--- /dev/null
+++ b/test_regress/t/t_lint_import_name2_bad.out
@@ -0,0 +1,7 @@
+%Error: t/t_lint_import_name2_bad.v:7:8: Importing from missing package 'missing'
+    7 | import missing::sigs;
+      |        ^~~~~~~
+%Error: t/t_lint_import_name2_bad.v:9:8: Importing from missing package 'missing'
+    9 | import missing::*;
+      |        ^~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_lint_import_name2_bad.pl b/test_regress/t/t_lint_import_name2_bad.pl
new file mode 100755
index 000000000..7539b1bd9
--- /dev/null
+++ b/test_regress/t/t_lint_import_name2_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_lint_import_name2_bad.v b/test_regress/t/t_lint_import_name2_bad.v
new file mode 100644
index 000000000..62b8845c8
--- /dev/null
+++ b/test_regress/t/t_lint_import_name2_bad.v
@@ -0,0 +1,9 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2018 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+import missing::sigs;
+
+import missing::*;