From ff360738b523aec19d0370d5921e8c981d063271 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 12 Jun 2019 07:19:14 -0400
Subject: [PATCH] XML: Remove extranious space on dtypes.

---
 src/V3EmitXml.cpp              |  2 +-
 test_regress/t/t_xml_first.out |  4 ++--
 test_regress/t/t_xml_tag.out   | 16 ++++++++--------
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/V3EmitXml.cpp b/src/V3EmitXml.cpp
index 79d2718b6..0f1f7435e 100644
--- a/src/V3EmitXml.cpp
+++ b/src/V3EmitXml.cpp
@@ -161,7 +161,7 @@ class EmitXmlFileVisitor : public AstNVisitor {
 
     // Data types
     virtual void visit(AstBasicDType* nodep) {
-        outputTag(nodep, "basicdtype ");
+        outputTag(nodep, "basicdtype");
         if (nodep->isRanged()) {
             puts(" left=\""+cvtToStr(nodep->left())+"\"");
             puts(" right=\""+cvtToStr(nodep->right())+"\"");
diff --git a/test_regress/t/t_xml_first.out b/test_regress/t/t_xml_first.out
index 22f21a67a..f535d8976 100644
--- a/test_regress/t/t_xml_first.out
+++ b/test_regress/t/t_xml_first.out
@@ -72,8 +72,8 @@
       </contassign>
     </module>
     <typetable fl="a0">
-      <basicdtype  fl="e46" id="1" name="logic"/>
-      <basicdtype  fl="e13" id="2" name="logic" left="3" right="0"/>
+      <basicdtype fl="e46" id="1" name="logic"/>
+      <basicdtype fl="e13" id="2" name="logic" left="3" right="0"/>
     </typetable>
   </netlist>
 </verilator_xml>
diff --git a/test_regress/t/t_xml_tag.out b/test_regress/t/t_xml_tag.out
index 136a38426..3c215a08f 100644
--- a/test_regress/t/t_xml_tag.out
+++ b/test_regress/t/t_xml_tag.out
@@ -56,19 +56,19 @@
       </modport>
     </iface>
     <typetable fl="a0">
-      <basicdtype  fl="e30" id="5" name="logic" left="31" right="0"/>
-      <basicdtype  fl="e7" id="6" name="integer" left="31" right="0"/>
-      <basicdtype  fl="e13" id="1" name="logic"/>
+      <basicdtype fl="e30" id="5" name="logic" left="31" right="0"/>
+      <basicdtype fl="e7" id="6" name="integer" left="31" right="0"/>
+      <basicdtype fl="e13" id="1" name="logic"/>
       <structdtype fl="e19" id="2" name="m.my_struct">
         <memberdtype fl="e20" id="8" name="clk" tag="this is clk" sub_dtype_id="9"/>
         <memberdtype fl="e21" id="10" name="k" sub_dtype_id="11"/>
         <memberdtype fl="e22" id="12" name="enable" tag="enable" sub_dtype_id="13"/>
         <memberdtype fl="e23" id="14" name="data" tag="data" sub_dtype_id="15"/>
       </structdtype>
-      <basicdtype  fl="e20" id="9" name="logic"/>
-      <basicdtype  fl="e21" id="11" name="logic"/>
-      <basicdtype  fl="e22" id="13" name="logic"/>
-      <basicdtype  fl="e23" id="15" name="logic"/>
+      <basicdtype fl="e20" id="9" name="logic"/>
+      <basicdtype fl="e21" id="11" name="logic"/>
+      <basicdtype fl="e22" id="13" name="logic"/>
+      <basicdtype fl="e23" id="15" name="logic"/>
       <ifacerefdtype fl="e28" id="3" modportname=""/>
       <unpackarraydtype fl="e30" id="4" sub_dtype_id="2">
         <range fl="e30">
@@ -77,7 +77,7 @@
         </range>
       </unpackarraydtype>
       <refdtype fl="e30" id="16" name="my_struct" sub_dtype_id="2"/>
-      <basicdtype  fl="e34" id="7" name="string"/>
+      <basicdtype fl="e34" id="7" name="string"/>
     </typetable>
   </netlist>
 </verilator_xml>