From ff262fc4fbfa68127d44fadf6cb2402413d25580 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 28 Nov 2020 17:29:21 -0500
Subject: [PATCH] Support type(t) static casting

---
 src/verilog.y           | 2 ++
 test_regress/t/t_type.v | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/verilog.y b/src/verilog.y
index e77ea9086..7026be4bd 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -4219,6 +4219,8 @@ expr<nodep>:			// IEEE: part of expression/constant_expression/primary
 	//			// IEEE: cast/constant_cast
 	//			// expanded from casting_type
 	|	simple_type yP_TICK '(' expr ')'	{ $$ = new AstCast($1->fileline(), $4, $1); }
+	|	yTYPE '(' exprOrDataType ')' yP_TICK '(' expr ')'
+			{ $$ = new AstCast($1, $7, new AstRefDType($1, AstRefDType::FlagTypeOfExpr(), $3)); }
 	|	ySIGNED yP_TICK '(' expr ')'		{ $$ = new AstSigned($1, $4); }
 	|	yUNSIGNED yP_TICK '(' expr ')'		{ $$ = new AstUnsigned($1, $4); }
 	|	ySTRING yP_TICK '(' expr ')'		{ $$ = new AstCvtPackString($1, $4); }
diff --git a/test_regress/t/t_type.v b/test_regress/t/t_type.v
index bb8bd852a..ce40dee79 100644
--- a/test_regress/t/t_type.v
+++ b/test_regress/t/t_type.v
@@ -15,6 +15,8 @@ module t(/*AUTOARG*/);
       y = 2.3;
       z = x + y;
       if (z != (1.2+2.3)) $stop;
+      z = type(z)'(22);
+      if (z != 22.0) $stop;
       $write("*-* All Finished *-*\n");
       $finish;
    end