diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index a99da06d3..c96d8ad86 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -1210,6 +1210,7 @@ sub _make_main {
     }
     print $fh "    Verilated::commandArgs(argc, argv);\n";
     print $fh "    Verilated::debug(".($self->{verilated_debug}?1:0).");\n";
+    print $fh "    srand48(5);\n";  # Ensure determinism
     print $fh "    Verilated::randReset(".$self->{verilated_randReset}.");\n" if defined $self->{verilated_randReset};
     print $fh "    topp = new $VM_PREFIX (\"top\");\n";
     my $set;
diff --git a/test_regress/t/t_mem_func.v b/test_regress/t/t_mem_func.v
index 106b36b27..972dfe4b9 100644
--- a/test_regress/t/t_mem_func.v
+++ b/test_regress/t/t_mem_func.v
@@ -116,8 +116,8 @@ module Test
 	 p[1]  = p1;
 	 p[2]  = p2;
 	 p[3]  = p3;
-	 p1_r[0] = p[0];
-	 p1_r[1] = p[1];
+         p1_r[0] <= p[0];
+         p1_r[1] <= p[1];
       end
    endtask
 endmodule