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Fix class reference with pin that is a class reference (#5454).
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@ -44,6 +44,7 @@ Verilator 5.029 devel
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* Fix driving clocking block in reactive region (#5430). [Krzysztof Bieganski, Antmicro Ltd.]
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* Fix associative array next/prev/first/last mis-propagating constants (#5435). [Ethan Sifferman]
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* Fix fault on defparam with UNSUPPORTED ignored (#5450). [Luiza de Melo]
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* Fix class reference with pin that is a class reference (#5454).
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Verilator 5.028 2024-08-21
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@ -2414,6 +2414,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
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void visit(AstCell* nodep) override {
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// Cell: Recurse inside or cleanup not founds
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checkNoDot(nodep);
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VL_RESTORER(m_usedPins);
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m_usedPins.clear();
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UASSERT_OBJ(nodep->modp(), nodep,
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"Cell has unlinked module"); // V3LinkCell should have errored out
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@ -2443,6 +2444,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
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void visit(AstClassRefDType* nodep) override {
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// Cell: Recurse inside or cleanup not founds
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checkNoDot(nodep);
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VL_RESTORER(m_usedPins);
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m_usedPins.clear();
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UASSERT_OBJ(nodep->classp(), nodep, "ClassRef has unlinked class");
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UASSERT_OBJ(m_statep->forPrimary() || !nodep->paramsp(), nodep,
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@ -3054,6 +3056,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
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void visit(AstClassOrPackageRef* nodep) override {
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// Class: Recurse inside or cleanup not founds
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// checkNoDot not appropriate, can be under a dot
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VL_RESTORER(m_usedPins);
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m_usedPins.clear();
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UASSERT_OBJ(m_statep->forPrimary() || VN_IS(nodep->classOrPackageNodep(), ParamTypeDType)
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|| nodep->classOrPackagep(),
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@ -4002,6 +4005,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
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UASSERT_OBJ(ifacep, nodep, "Port parameters of AstIfaceRefDType without ifacep()");
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if (ifacep->dead()) return;
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checkNoDot(nodep);
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VL_RESTORER(m_usedPins);
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m_usedPins.clear();
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VL_RESTORER(m_pinSymp);
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m_pinSymp = m_statep->getNodeSym(ifacep);
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16
test_regress/t/t_class_ref_ref.py
Executable file
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test_regress/t/t_class_ref_ref.py
Executable file
@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.lint()
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test.passes()
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test_regress/t/t_class_ref_ref.v
Normal file
21
test_regress/t/t_class_ref_ref.v
Normal file
@ -0,0 +1,21 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls#(type T = bit);
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endclass
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module t(/*AUTOARG*/);
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Cls#(bit) cb;
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Cls#(Cls#(bit)) ccb;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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