Fix fault on empty clocking block (#4593).

Changes

@@ -44,6 +44,7 @@ Verilator 5.017 devel
 * Fix compile warning on unused member function variable (#4567).
 * Fix method narrowing conversion compiler error (#4568).
 * Fix display optimization ignoring side effects (#4585).
+* Fix fault on empty clocking block (#4593). [Alex Mykyta]
 * Fix preprocessor to show `line 2 on resumed file.
 
 

src/V3SchedTiming.cpp

@@ -395,7 +395,11 @@ void transformForks(AstNetlist* const netlistp) {
             } else {
                 // The begin has neither awaits nor a process::self call, just inline the
                 // statements
-                nodep->replaceWith(nodep->stmtsp()->unlinkFrBackWithNext());
+                if (nodep->stmtsp()) {
+                    nodep->replaceWith(nodep->stmtsp()->unlinkFrBackWithNext());
+                } else {
+                    nodep->unlinkFrBack();
+                }
             }
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         }

test_regress/t/t_clocking_empty_block.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--exe --main --timing"],
+    make_main => 0,
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_clocking_empty_block.v

@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Alex Mykyta.
+// SPDX-License-Identifier: CC0-1.0
+
+module t();
+   logic clk = 0;
+   logic x;
+   logic y;
+   always #1ns clk = ~clk;
+   clocking cb @(posedge clk);
+      output #1ns x;
+      input  #1step y;
+   endclocking
+   initial begin
+      repeat(10) @(posedge clk);
+      $display("*-* All Finished *-*");
+      $finish();
+   end
+endmodule