diff --git a/Changes b/Changes
index 2445192bc..2bff83d78 100644
--- a/Changes
+++ b/Changes
@@ -49,6 +49,7 @@ Verilator 5.025 devel
 * Fix method calls parsing in constraints (#5110). [Arkadiusz Kozdra, Antmicro Ltd.]
 * Fix vpiInertialDelay for memories (#5113). [Todd Strader]
 * Fix references to ports in forks (#5123). [Krzysztof Bieganski, Antmicro Ltd.]
+* Fix x-valued parameters with `--x-assign unique` (#5129). [Ethan Sifferman]
 
 
 Verilator 5.024 2024-04-05
diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst
index 453baa1ab..237671b5b 100644
--- a/docs/guide/exe_verilator.rst
+++ b/docs/guide/exe_verilator.rst
@@ -1744,9 +1744,9 @@ Summary:
 
    .. note::
 
-      This option applies only to values explicitly written as X
-      in modules (not classes) in the Verilog source code. Initial values
-      of clocks are set to 0 unless `--x-initial-edge` is
+      This option applies only to values explicitly written as X in modules
+      (not classes, nor parameters) in the Verilog source code. Initial
+      values of clocks are set to 0 unless `--x-initial-edge` is
       specified. Initial values of all other state holding variables are
       controlled with `--x-initial`.
 
diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp
index 43617e72c..4d7e57e23 100644
--- a/src/V3Unknown.cpp
+++ b/src/V3Unknown.cpp
@@ -192,6 +192,11 @@ class UnknownVisitor final : public VNVisitor {
             iterateChildren(nodep);
         }
     }
+    void visit(AstVar* nodep) override {
+        VL_RESTORER(m_allowXUnique);
+        if (nodep->isParam()) m_allowXUnique = false;
+        iterateChildren(nodep);
+    }
     void visitEqNeqCase(AstNodeBiop* nodep) {
         UINFO(4, " N/EQCASE->EQ " << nodep << endl);
         V3Const::constifyEdit(nodep->lhsp());  // lhsp may change
diff --git a/test_regress/t/t_param_x_unique.pl b/test_regress/t/t_param_x_unique.pl
new file mode 100755
index 000000000..688171716
--- /dev/null
+++ b/test_regress/t/t_param_x_unique.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--trace-fst --x-assign unique"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_param_x_unique.v b/test_regress/t/t_param_x_unique.v
new file mode 100644
index 000000000..feeb4c2c7
--- /dev/null
+++ b/test_regress/t/t_param_x_unique.v
@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module sub #(parameter P = 1'bx);
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+module t;
+   sub sub();
+endmodule