mirror of
https://github.com/verilator/verilator.git
synced 2025-01-01 04:07:34 +00:00
Internals: Standardize internal FileLine filenames.
This commit is contained in:
Wilson Snyder
parent
2cedd14d43
commit
f7f73a0825
@ -124,6 +124,8 @@ public:
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V3LangCode language() const { return singleton().numberToLang(m_filenameno); }
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string ascii() const;
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const string filename() const { return singleton().numberToName(m_filenameno); }
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bool filenameIsGlobal() const { return (filename() == commandLineFilename()
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|| filename() == internalDefineFilename()); }
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const string filenameLetters() const { return singleton().filenameLetters(m_filenameno); }
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const string filebasename() const;
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const string filebasenameNoExt() const;
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@ -147,6 +149,8 @@ public:
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void tracingOn(bool flag) { warnOn(V3ErrorCode::I_TRACING, flag); }
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// METHODS - Global
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static string commandLineFilename() { return "COMMAND_LINE"; }
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static string internalDefineFilename() { return "INTERNAL_VERILATOR_DEFINE"; }
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static void globalWarnLintOff(bool flag) {
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defaultFileLine().warnLintOff(flag); }
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static void globalWarnStyleOff(bool flag) {
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@ -60,11 +60,11 @@ protected:
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// Create the implementation pointer
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if (env) {}
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if (!s_preprocp) {
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FileLine* cmdfl = new FileLine("COMMAND_LINE", 0);
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FileLine* cmdfl = new FileLine(FileLine::commandLineFilename(), 0);
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s_preprocp = V3PreProc::createPreProc(cmdfl);
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s_preprocp->debug(debug());
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// Default defines
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FileLine* prefl = new FileLine("INTERNAL_VERILATOR_DEFINE", 0);
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FileLine* prefl = new FileLine(FileLine::internalDefineFilename(), 0);
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s_preprocp->defineCmdLine(prefl, "VERILATOR", "1"); // LEAK_OK
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s_preprocp->defineCmdLine(prefl, "verilator", "1"); // LEAK_OK
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s_preprocp->defineCmdLine(prefl, "verilator3", "1"); // LEAK_OK
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@ -178,7 +178,7 @@ void V3PreShell::preprocInclude(FileLine* fl, const string& modname) {
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V3PreShellImp::s_preImp.preprocInclude(fl, modname);
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}
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void V3PreShell::defineCmdLine(const string& name, const string& value) {
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FileLine* prefl = new FileLine("COMMAND_LINE_DEFINE", 0);
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FileLine* prefl = new FileLine(FileLine::commandLineFilename(), 0);
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V3PreShellImp::s_preprocp->defineCmdLine(prefl, name, value);
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}
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void V3PreShell::undef(const string& name) {
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@ -127,7 +127,8 @@ void V3Global::readFiles() {
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const V3StringList& vFiles = v3Global.opt.vFiles();
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for (V3StringList::const_iterator it = vFiles.begin(); it != vFiles.end(); ++it) {
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string filename = *it;
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parser.parseFile(new FileLine("COMMAND_LINE", 0), filename, false,
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parser.parseFile(new FileLine(FileLine::commandLineFilename(), 0),
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filename, false,
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"Cannot find file containing module: ");
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}
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@ -137,7 +138,8 @@ void V3Global::readFiles() {
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const V3StringSet& libraryFiles = v3Global.opt.libraryFiles();
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for (V3StringSet::const_iterator it = libraryFiles.begin(); it != libraryFiles.end(); ++it) {
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string filename = *it;
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parser.parseFile(new FileLine("COMMAND_LINE", 0), filename, true,
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parser.parseFile(new FileLine(FileLine::commandLineFilename(), 0),
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filename, true,
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"Cannot find file containing library module: ");
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}
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//v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("parse.tree"));
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@ -582,7 +584,8 @@ int main(int argc, char** argv, char** env) {
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// Command option parsing
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v3Global.opt.bin(argv[0]);
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string argString = V3Options::argString(argc-1, argv+1);
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v3Global.opt.parseOpts(new FileLine("COMMAND_LINE", 0), argc-1, argv+1);
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v3Global.opt.parseOpts(new FileLine(FileLine::commandLineFilename(), 0),
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argc-1, argv+1);
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if (!v3Global.opt.outFormatOk()
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&& !v3Global.opt.preprocOnly()
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&& !v3Global.opt.lintOnly()
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@ -4,77 +4,76 @@
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<files>
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<file id="a" filename="AstRoot" language="1800-2017"/>
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<file id="b" filename="COMMAND_LINE" language="1800-2017"/>
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<file id="e" filename="COMMAND_LINE_DEFINE" language="1800-2017"/>
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<file id="c" filename="INTERNAL_VERILATOR_DEFINE" language="1800-2017"/>
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<file id="d" filename="input.vc" language="1800-2017"/>
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<file id="f" filename="t/t_xml_first.v" language="1800-2017"/>
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<file id="e" filename="t/t_xml_first.v" language="1800-2017"/>
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</files>
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<module_files>
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<file id="f" filename="t/t_xml_first.v" language="1800-2017"/>
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<file id="e" filename="t/t_xml_first.v" language="1800-2017"/>
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</module_files>
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<cells>
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<cell fl="f6" name="t" submodname="t" hier="t">
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<cell fl="f18" name="cell1" submodname="mod1" hier="t.cell1"/>
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<cell fl="f24" name="cell2" submodname="mod2" hier="t.cell2"/>
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<cell fl="e6" name="t" submodname="t" hier="t">
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<cell fl="e18" name="cell1" submodname="mod1" hier="t.cell1"/>
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<cell fl="e24" name="cell2" submodname="mod2" hier="t.cell2"/>
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</cell>
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</cells>
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<netlist>
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<module fl="f6" name="t" origName="t" topModule="1">
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<var fl="f12" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="f13" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="f14" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<var fl="f16" name="between" dtype_id="2" vartype="logic" origName="between"/>
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<instance fl="f18" name="cell1" defName="mod1" origName="cell1">
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<port fl="f18" name="q" direction="out" portIndex="1">
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<varref fl="f18" name="between" dtype_id="2"/>
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<module fl="e6" name="t" origName="t" topModule="1">
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<var fl="e12" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="e13" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="e14" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<var fl="e16" name="between" dtype_id="2" vartype="logic" origName="between"/>
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<instance fl="e18" name="cell1" defName="mod1" origName="cell1">
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<port fl="e18" name="q" direction="out" portIndex="1">
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<varref fl="e18" name="between" dtype_id="2"/>
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</port>
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<port fl="f21" name="clk" direction="in" portIndex="2">
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<varref fl="f21" name="clk" dtype_id="1"/>
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<port fl="e21" name="clk" direction="in" portIndex="2">
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<varref fl="e21" name="clk" dtype_id="1"/>
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</port>
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<port fl="f22" name="d" direction="in" portIndex="3">
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<varref fl="f22" name="d" dtype_id="2"/>
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<port fl="e22" name="d" direction="in" portIndex="3">
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<varref fl="e22" name="d" dtype_id="2"/>
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</port>
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</instance>
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<instance fl="f24" name="cell2" defName="mod2" origName="cell2">
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<port fl="f24" name="d" direction="in" portIndex="1">
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<varref fl="f24" name="between" dtype_id="2"/>
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<instance fl="e24" name="cell2" defName="mod2" origName="cell2">
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<port fl="e24" name="d" direction="in" portIndex="1">
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<varref fl="e24" name="between" dtype_id="2"/>
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</port>
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<port fl="f27" name="q" direction="out" portIndex="2">
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<varref fl="f27" name="q" dtype_id="2"/>
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<port fl="e27" name="q" direction="out" portIndex="2">
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<varref fl="e27" name="q" dtype_id="2"/>
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</port>
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<port fl="f29" name="clk" direction="in" portIndex="3">
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<varref fl="f29" name="clk" dtype_id="1"/>
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<port fl="e29" name="clk" direction="in" portIndex="3">
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<varref fl="e29" name="clk" dtype_id="1"/>
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</port>
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</instance>
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</module>
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<module fl="f33" name="mod1" origName="mod1">
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<var fl="f35" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="f36" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="f37" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<always fl="f39">
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<sentree fl="f39">
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<senitem fl="f39" edgeType="POS">
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<varref fl="f39" name="clk" dtype_id="1"/>
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<module fl="e33" name="mod1" origName="mod1">
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<var fl="e35" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="e36" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="e37" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<always fl="e39">
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<sentree fl="e39">
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<senitem fl="e39" edgeType="POS">
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<varref fl="e39" name="clk" dtype_id="1"/>
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</senitem>
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</sentree>
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<assigndly fl="f40" dtype_id="2">
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<varref fl="f40" name="d" dtype_id="2"/>
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<varref fl="f40" name="q" dtype_id="2"/>
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<assigndly fl="e40" dtype_id="2">
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<varref fl="e40" name="d" dtype_id="2"/>
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<varref fl="e40" name="q" dtype_id="2"/>
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</assigndly>
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</always>
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</module>
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<module fl="f44" name="mod2" origName="mod2">
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<var fl="f46" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="f47" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="f48" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<contassign fl="f51" dtype_id="2">
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<varref fl="f51" name="d" dtype_id="2"/>
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<varref fl="f51" name="q" dtype_id="2"/>
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<module fl="e44" name="mod2" origName="mod2">
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<var fl="e46" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="e47" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="e48" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<contassign fl="e51" dtype_id="2">
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<varref fl="e51" name="d" dtype_id="2"/>
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<varref fl="e51" name="q" dtype_id="2"/>
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</contassign>
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</module>
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<typetable fl="a0">
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<basicdtype fl="f46" id="1" name="logic"/>
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<basicdtype fl="f13" id="2" name="logic" left="3" right="0"/>
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<basicdtype fl="e46" id="1" name="logic"/>
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<basicdtype fl="e13" id="2" name="logic" left="3" right="0"/>
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</typetable>
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</netlist>
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</verilator_xml>
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@ -4,81 +4,80 @@
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<files>
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<file id="a" filename="AstRoot" language="1800-2017"/>
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<file id="b" filename="COMMAND_LINE" language="1800-2017"/>
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<file id="e" filename="COMMAND_LINE_DEFINE" language="1800-2017"/>
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<file id="c" filename="INTERNAL_VERILATOR_DEFINE" language="1800-2017"/>
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<file id="d" filename="input.vc" language="1800-2017"/>
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<file id="f" filename="t/t_xml_tag.v" language="1800-2017"/>
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<file id="e" filename="t/t_xml_tag.v" language="1800-2017"/>
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</files>
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<module_files>
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<file id="f" filename="t/t_xml_tag.v" language="1800-2017"/>
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<file id="e" filename="t/t_xml_tag.v" language="1800-2017"/>
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</module_files>
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<cells>
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<cell fl="f11" name="m" submodname="m" hier="m">
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<cell fl="f28" name="itop" submodname="ifc" hier="m.itop"/>
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<cell fl="e11" name="m" submodname="m" hier="m">
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<cell fl="e28" name="itop" submodname="ifc" hier="m.itop"/>
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</cell>
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</cells>
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<netlist>
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<module fl="f11" name="m" origName="m" topModule="1">
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<var fl="f13" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" vartype="logic" origName="clk_ip"/>
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<var fl="f14" name="rst_ip" dtype_id="1" dir="input" vartype="logic" origName="rst_ip"/>
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<var fl="f15" name="foo_op" tag="foo_op" dtype_id="1" dir="output" vartype="logic" origName="foo_op"/>
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<typedef fl="f19" name="my_struct" tag="my_struct" dtype_id="2"/>
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<instance fl="f28" name="itop" defName="ifc" origName="itop"/>
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<var fl="f28" name="itop__Viftop" dtype_id="3" vartype="ifaceref" origName="itop__Viftop"/>
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<var fl="f30" name="this_struct" tag="this_struct" dtype_id="4" vartype="" origName="this_struct"/>
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<var fl="f32" name="dotted" dtype_id="5" vartype="logic" origName="dotted"/>
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<contassign fl="f32" dtype_id="5">
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<varxref fl="f32" name="value" dtype_id="6" dotted="itop"/>
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<varref fl="f32" name="dotted" dtype_id="5"/>
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<module fl="e11" name="m" origName="m" topModule="1">
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<var fl="e13" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" vartype="logic" origName="clk_ip"/>
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<var fl="e14" name="rst_ip" dtype_id="1" dir="input" vartype="logic" origName="rst_ip"/>
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<var fl="e15" name="foo_op" tag="foo_op" dtype_id="1" dir="output" vartype="logic" origName="foo_op"/>
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<typedef fl="e19" name="my_struct" tag="my_struct" dtype_id="2"/>
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<instance fl="e28" name="itop" defName="ifc" origName="itop"/>
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<var fl="e28" name="itop__Viftop" dtype_id="3" vartype="ifaceref" origName="itop__Viftop"/>
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<var fl="e30" name="this_struct" tag="this_struct" dtype_id="4" vartype="" origName="this_struct"/>
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<var fl="e32" name="dotted" dtype_id="5" vartype="logic" origName="dotted"/>
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<contassign fl="e32" dtype_id="5">
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<varxref fl="e32" name="value" dtype_id="6" dotted="itop"/>
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<varref fl="e32" name="dotted" dtype_id="5"/>
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</contassign>
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<func fl="f34" name="f" dtype_id="1">
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<var fl="f34" name="f" dtype_id="1" dir="output" vartype="logic" origName="f"/>
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<var fl="f34" name="m" dtype_id="7" dir="input" vartype="string" origName="m"/>
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<display fl="f35" displaytype="$display">
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<sformatf fl="f35" name="%@" dtype_id="7">
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<varref fl="f35" name="m" dtype_id="7"/>
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<func fl="e34" name="f" dtype_id="1">
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<var fl="e34" name="f" dtype_id="1" dir="output" vartype="logic" origName="f"/>
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<var fl="e34" name="m" dtype_id="7" dir="input" vartype="string" origName="m"/>
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<display fl="e35" displaytype="$display">
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<sformatf fl="e35" name="%@" dtype_id="7">
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<varref fl="e35" name="m" dtype_id="7"/>
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</sformatf>
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</display>
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</func>
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<initial fl="f38">
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<begin fl="f38">
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<taskref fl="f40" name="f">
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<arg fl="f40">
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<const fl="f40" name=""	   !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~€‚ƒ„…†‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›œžŸ ¡¢£¤¥¦§¨©ª«¬­®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿ"" dtype_id="7"/>
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<initial fl="e38">
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<begin fl="e38">
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<taskref fl="e40" name="f">
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<arg fl="e40">
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<const fl="e40" name=""	   !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~€‚ƒ„…†‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›œžŸ ¡¢£¤¥¦§¨©ª«¬­®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿ"" dtype_id="7"/>
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</arg>
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</taskref>
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</begin>
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</initial>
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</module>
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<iface fl="f6" name="ifc" origName="ifc">
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<var fl="f7" name="value" dtype_id="6" vartype="integer" origName="value"/>
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<modport fl="f8" name="out_modport">
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<modportvarref fl="f8" name="value" direction="out"/>
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<iface fl="e6" name="ifc" origName="ifc">
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<var fl="e7" name="value" dtype_id="6" vartype="integer" origName="value"/>
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<modport fl="e8" name="out_modport">
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<modportvarref fl="e8" name="value" direction="out"/>
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</modport>
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</iface>
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<typetable fl="a0">
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<basicdtype fl="f30" id="5" name="logic" left="31" right="0"/>
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<basicdtype fl="f7" id="6" name="integer" left="31" right="0"/>
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<basicdtype fl="f13" id="1" name="logic"/>
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<structdtype fl="f19" id="2" name="m.my_struct">
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<memberdtype fl="f20" id="8" name="clk" tag="this is clk" sub_dtype_id="9"/>
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<memberdtype fl="f21" id="10" name="k" sub_dtype_id="11"/>
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<memberdtype fl="f22" id="12" name="enable" tag="enable" sub_dtype_id="13"/>
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<memberdtype fl="f23" id="14" name="data" tag="data" sub_dtype_id="15"/>
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<basicdtype fl="e30" id="5" name="logic" left="31" right="0"/>
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<basicdtype fl="e7" id="6" name="integer" left="31" right="0"/>
|
||||
<basicdtype fl="e13" id="1" name="logic"/>
|
||||
<structdtype fl="e19" id="2" name="m.my_struct">
|
||||
<memberdtype fl="e20" id="8" name="clk" tag="this is clk" sub_dtype_id="9"/>
|
||||
<memberdtype fl="e21" id="10" name="k" sub_dtype_id="11"/>
|
||||
<memberdtype fl="e22" id="12" name="enable" tag="enable" sub_dtype_id="13"/>
|
||||
<memberdtype fl="e23" id="14" name="data" tag="data" sub_dtype_id="15"/>
|
||||
</structdtype>
|
||||
<basicdtype fl="f20" id="9" name="logic"/>
|
||||
<basicdtype fl="f21" id="11" name="logic"/>
|
||||
<basicdtype fl="f22" id="13" name="logic"/>
|
||||
<basicdtype fl="f23" id="15" name="logic"/>
|
||||
<ifacerefdtype fl="f28" id="3" modportname=""/>
|
||||
<unpackarraydtype fl="f30" id="4" sub_dtype_id="2">
|
||||
<range fl="f30">
|
||||
<const fl="f30" name="32'h1" dtype_id="5"/>
|
||||
<const fl="f30" name="32'h0" dtype_id="5"/>
|
||||
<basicdtype fl="e20" id="9" name="logic"/>
|
||||
<basicdtype fl="e21" id="11" name="logic"/>
|
||||
<basicdtype fl="e22" id="13" name="logic"/>
|
||||
<basicdtype fl="e23" id="15" name="logic"/>
|
||||
<ifacerefdtype fl="e28" id="3" modportname=""/>
|
||||
<unpackarraydtype fl="e30" id="4" sub_dtype_id="2">
|
||||
<range fl="e30">
|
||||
<const fl="e30" name="32'h1" dtype_id="5"/>
|
||||
<const fl="e30" name="32'h0" dtype_id="5"/>
|
||||
</range>
|
||||
</unpackarraydtype>
|
||||
<refdtype fl="f30" id="16" name="my_struct" sub_dtype_id="2"/>
|
||||
<basicdtype fl="f34" id="7" name="string"/>
|
||||
<refdtype fl="e30" id="16" name="my_struct" sub_dtype_id="2"/>
|
||||
<basicdtype fl="e34" id="7" name="string"/>
|
||||
</typetable>
|
||||
</netlist>
|
||||
</verilator_xml>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user