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emacs verilog-batch-indent

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This commit is contained in:
Todd Strader 2020-02-21 05:50:09 -05:00
parent 4b4f10f5e6
commit f7d1c6ca72
2 changed files with 44 additions and 44 deletions
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24
test_regress/t/t_prot_lib.v
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@ -15,16 +15,16 @@ if (cyc > 0 && sig``_in != sig``_out) begin \
end
module t #(parameter GATED_CLK = 0) (/*AUTOARG*/
// Inputs
clk
);
// Inputs
clk
);
input clk;
localparam last_cyc =
`ifdef TEST_BENCHMARK
`TEST_BENCHMARK;
`TEST_BENCHMARK;
`else
10;
10;
`endif
genvar x;
@ -55,7 +55,7 @@ module t #(parameter GATED_CLK = 0) (/*AUTOARG*/
logic [3:0] [31:0] s4x32_in;
logic [3:0] [31:0] s4x32_out;
wire clk_en = crc[0];
wire clk_en = crc[0];
secret
secret (
@ -125,13 +125,13 @@ module t #(parameter GATED_CLK = 0) (/*AUTOARG*/
logic possibly_gated_clk;
if (GATED_CLK != 0) begin: yes_gated_clock
logic clk_en_latch /*verilator clock_enable*/;
/* verilator lint_off COMBDLY */
always_comb if (clk == '0) clk_en_latch <= clk_en;
/* verilator lint_on COMBDLY */
assign possibly_gated_clk = clk & clk_en_latch;
logic clk_en_latch /*verilator clock_enable*/;
/* verilator lint_off COMBDLY */
always_comb if (clk == '0) clk_en_latch <= clk_en;
/* verilator lint_on COMBDLY */
assign possibly_gated_clk = clk & clk_en_latch;
end else begin: no_gated_clock
assign possibly_gated_clk = clk;
assign possibly_gated_clk = clk;
end
always @(posedge possibly_gated_clk) begin

64
test_regress/t/t_prot_lib_secret.v
View File

@ -3,45 +3,45 @@
// without warranty, 2019 by Todd Strader.
module secret #(parameter GATED_CLK = 0)
(
input [31:0] accum_in,
output wire [31:0] accum_out,
input accum_bypass,
output [31:0] accum_bypass_out,
input s1_in,
output logic s1_out,
input [1:0] s2_in,
output logic [1:0] s2_out,
input [7:0] s8_in,
output logic [7:0] s8_out,
input [32:0] s33_in,
output logic [32:0] s33_out,
input [63:0] s64_in,
output logic [63:0] s64_out,
input [64:0] s65_in,
output logic [64:0] s65_out,
input [128:0] s129_in,
output logic [128:0] s129_out,
input [3:0] [31:0] s4x32_in,
output logic [3:0] [31:0] s4x32_out,
input clk_en,
input clk /*verilator clocker*/);
(
input [31:0] accum_in,
output wire [31:0] accum_out,
input accum_bypass,
output [31:0] accum_bypass_out,
input s1_in,
output logic s1_out,
input [1:0] s2_in,
output logic [1:0] s2_out,
input [7:0] s8_in,
output logic [7:0] s8_out,
input [32:0] s33_in,
output logic [32:0] s33_out,
input [63:0] s64_in,
output logic [63:0] s64_out,
input [64:0] s65_in,
output logic [64:0] s65_out,
input [128:0] s129_in,
output logic [128:0] s129_out,
input [3:0] [31:0] s4x32_in,
output logic [3:0] [31:0] s4x32_out,
input clk_en,
input clk /*verilator clocker*/);
logic [31:0] secret_accum_q = 0;
logic [31:0] secret_value = 7;
logic [31:0] secret_accum_q = 0;
logic [31:0] secret_value = 7;
initial $display("created %m");
logic the_clk;
logic the_clk;
generate
if (GATED_CLK != 0) begin: yes_gated_clock
logic clk_en_latch /*verilator clock_enable*/;
/* verilator lint_off COMBDLY */
always_comb if (clk == '0) clk_en_latch <= clk_en;
/* verilator lint_on COMBDLY */
assign the_clk = clk & clk_en_latch;
logic clk_en_latch /*verilator clock_enable*/;
/* verilator lint_off COMBDLY */
always_comb if (clk == '0) clk_en_latch <= clk_en;
/* verilator lint_on COMBDLY */
assign the_clk = clk & clk_en_latch;
end else begin: no_gated_clock
assign the_clk = clk;
assign the_clk = clk;
end
endgenerate