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tests: GHDL test driver support
This commit is contained in:
Wilson Snyder
parent
350ba264e8
commit
f6fab74436
@ -48,6 +48,7 @@ my @opt_tests;
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my $opt_gdb;
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my $opt_gdbbt;
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my $opt_gdbsim;
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my $opt_ghdl;
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my $opt_iv;
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my $opt_jobs = 1;
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my $opt_nc;
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@ -70,6 +71,7 @@ if (! GetOptions (
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"gdb!" => \$opt_gdb,
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"gdbbt!" => \$opt_gdbbt,
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"gdbsim!" => \$opt_gdbsim,
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"ghdl!" => \$opt_ghdl,
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"golden!" => sub { $ENV{HARNESS_UPDATE_GOLDEN} = 1; },
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"help" => \&usage,
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"iverilog!" => \$opt_iv,
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@ -95,7 +97,7 @@ $opt_jobs = calc_jobs() if defined $opt_jobs && $opt_jobs==0;
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$Fork->max_proc($opt_jobs);
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if (!$opt_atsim && !$opt_iv && !$opt_vcs && !$opt_nc && !$opt_vlt) {
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if (!$opt_atsim && !$opt_ghdl && !$opt_iv && !$opt_vcs && !$opt_nc && !$opt_vlt) {
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$opt_vlt = 1;
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}
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@ -120,6 +122,7 @@ my @fails;
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foreach my $testpl (@opt_tests) {
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one_test(pl_filename => $testpl, atsim=>1) if $opt_atsim;
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one_test(pl_filename => $testpl, ghdl=>1) if $opt_ghdl;
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one_test(pl_filename => $testpl, iv=>1) if $opt_iv;
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one_test(pl_filename => $testpl, nc=>1) if $opt_nc;
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one_test(pl_filename => $testpl, vcs=>1) if $opt_vcs;
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@ -306,6 +309,13 @@ sub new {
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"+sv_dir+$self->{obj_dir}/.athdl_compile"],
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atsim_flags2 => [], # Overridden in some sim files
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atsimrun_flags => [],
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# GHDL
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ghdl => 0,
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ghdl_work_dir => "$self->{obj_dir}/ghdl_compile",
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ghdl_flags => [($::Debug?"-v":""),
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"--workdir=$self->{obj_dir}/ghdl_compile", ],
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ghdl_flags2 => [], # Overridden in some sim files
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ghdlrun_flags => [],
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# IV
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iv => 0,
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iv_flags => [split(/\s+/,"+define+iverilog -o $self->{obj_dir}/simiv")],
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@ -335,6 +345,7 @@ sub new {
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bless $self, $class;
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$self->{mode} ||= "atsim" if $self->{atsim};
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$self->{mode} ||= "ghdl" if $self->{ghdl};
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$self->{mode} ||= "vcs" if $self->{vcs};
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$self->{mode} ||= "vlt" if $self->{vlt};
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$self->{mode} ||= "nc" if $self->{nc};
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@ -347,11 +358,6 @@ sub new {
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$self->{vcd_filename} ||= "$self->{obj_dir}/sim.vcd";
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$self->{main_filename} ||= "$self->{obj_dir}/$self->{VM_PREFIX}__main.cpp";
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($self->{top_filename} = $self->{pl_filename}) =~ s/\.pl$/\.v/;
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if (!$self->{make_top_shell}) {
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$self->{top_shell_filename} = $self->{top_filename};
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} else {
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$self->{top_shell_filename} = "$self->{obj_dir}/$self->{VM_PREFIX}__top.v";
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}
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return $self;
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}
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@ -392,7 +398,6 @@ sub read {
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(-r $self->{pl_filename})
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or return $self->error("Can't open $self->{pl_filename}\n");
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$Self = $self;
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$Self = $self;
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delete $INC{$self->{pl_filename}};
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require $self->{pl_filename};
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}
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@ -476,6 +481,14 @@ sub compile {
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compile_vlt_flags(%param);
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if (!$self->{make_top_shell}) {
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$param{top_shell_filename}
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= $self->{top_shell_filename} = $self->{top_filename};
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} else {
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$param{top_shell_filename}
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= $self->{top_shell_filename} = "$self->{obj_dir}/$self->{VM_PREFIX}__top.".$self->v_suffix;
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}
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if ($param{atsim}) {
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$self->_make_top();
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$self->_run(logfile=>"$self->{obj_dir}/atsim_compile.log",
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@ -490,7 +503,25 @@ sub compile {
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@{$param{v_other_filenames}},
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]);
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}
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if ($param{vcs}) {
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elsif ($param{ghdl}) {
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mkdir $self->{ghdl_work_dir};
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$self->_make_top();
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$self->_run(logfile=>"$self->{obj_dir}/ghdl_compile.log",
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fails=>$param{fails},
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cmd=>[($ENV{VERILATOR_GHDL}||"ghdl"),
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# Add -c here, as having -c twice freaks it out
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((($ENV{VERILATOR_GHDL}||' ') =~ / -c\b/) ? "" : "-c"),
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@{$param{ghdl_flags}},
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@{$param{ghdl_flags2}},
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#@{$param{v_flags}}, # Not supported
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#@{$param{v_flags2}}, # Not supported
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$param{top_filename},
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$param{top_shell_filename},
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@{$param{v_other_filenames}},
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"-e t",
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]);
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}
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elsif ($param{vcs}) {
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$self->_make_top();
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$self->_run(logfile=>"$self->{obj_dir}/vcs_compile.log",
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fails=>$param{fails},
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@ -504,8 +535,14 @@ sub compile {
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@{$param{v_other_filenames}},
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]);
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}
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if ($param{nc}) {
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elsif ($param{nc}) {
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$self->_make_top();
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my @more_args;
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if ($self->vhdl) {
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((my $ts = $param{top_shell_filename}) =~ s!\.v!!);
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$ts =~ s!.*/!!;;
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push @more_args, "-vhdltop", $ts;
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}
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$self->_run(logfile=>"$self->{obj_dir}/nc_compile.log",
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fails=>$param{fails},
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cmd=>[($ENV{VERILATOR_NCVERILOG}||"ncverilog"),
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@ -516,9 +553,10 @@ sub compile {
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$param{top_filename},
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$param{top_shell_filename},
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@{$param{v_other_filenames}},
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@more_args
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]);
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}
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if ($param{iv}) {
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elsif ($param{iv}) {
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$self->_make_top();
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my @cmd = (($ENV{VERILATOR_IVERILOG}||"iverilog"),
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@{$param{iv_flags}},
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@ -534,7 +572,7 @@ sub compile {
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fails=>$param{fails},
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cmd=>\@cmd);
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}
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if ($param{vlt}) {
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elsif ($param{vlt}) {
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my @cmdargs = $self->compile_vlt_flags(%param);
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if ($self->sc_or_sp && !defined $ENV{SYSTEMC}) {
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@ -575,6 +613,9 @@ sub compile {
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]);
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}
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}
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else {
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$self->error("No compile step for this simulator");
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}
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return 1;
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}
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@ -595,7 +636,15 @@ sub execute {
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@{$param{all_run_flags}},
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]);
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}
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if ($param{iv}) {
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elsif ($param{ghdl}) {
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$self->_run(logfile=>"$self->{obj_dir}/ghdl_sim.log",
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fails=>$param{fails},
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cmd=>[$run_env."$self->{obj_dir}/simghdl",
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@{$param{ghdlrun_flags}},
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@{$param{all_run_flags}},
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]);
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}
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elsif ($param{iv}) {
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$self->_run(logfile=>"$self->{obj_dir}/iv_sim.log",
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fails=>$param{fails},
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cmd=>[$run_env."$self->{obj_dir}/simiv",
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@ -603,7 +652,7 @@ sub execute {
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@{$param{all_run_flags}},
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]);
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}
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if ($param{nc}) {
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elsif ($param{nc}) {
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$self->_run(logfile=>"$self->{obj_dir}/nc_sim.log",
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fails=>$param{fails},
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cmd=>["echo q | ".$run_env.($ENV{VERILATOR_NCVERILOG}||"ncverilog"),
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@ -611,7 +660,7 @@ sub execute {
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@{$param{all_run_flags}},
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]);
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}
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if ($param{vcs}) {
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elsif ($param{vcs}) {
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#my $fh = IO::File->new(">simv.key") or die "%Error: $! simv.key,";
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#$fh->print("quit\n"); $fh->close;
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$self->_run(logfile=>"$self->{obj_dir}/vcs_sim.log",
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@ -623,7 +672,7 @@ sub execute {
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expect=>undef, # vcs expect isn't the same
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);
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}
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if ($param{vlt}
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elsif ($param{vlt}
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#&& (!$param{needs_v4} || -r "$ENV{VERILATOR_ROOT}/src/V3Gate.cpp")
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) {
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$param{executable} ||= "$self->{obj_dir}/$param{VM_PREFIX}";
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@ -636,6 +685,9 @@ sub execute {
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%param,
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);
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}
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else {
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$self->error("No execute step for this simulator");
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}
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}
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sub inline_checks {
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@ -705,6 +757,21 @@ sub top_filename {
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return $self->{top_filename};
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}
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sub vhdl {
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my $self = (ref $_[0]? shift : $Self);
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$self->{vhdl} = shift if defined $_[0];
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if ($self->{vhdl}) {
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$self->{top_filename} =~ s/\.v$/\.vhdl/;
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}
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return $self->{vhdl};
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}
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sub v_suffix {
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my $self = (ref $_[0]? shift : $Self);
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# Suffix for file type, e.g. .vhdl or .v
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return $self->{vhdl} ? "vhdl" : "v";
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}
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sub sp {
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my $self = (ref $_[0]? shift : $Self);
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return $self->{sp};
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@ -816,7 +883,11 @@ sub _run {
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sub _make_main {
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my $self = shift;
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$self->_read_inputs();
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if ($self->vhdl) {
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$self->_read_inputs_vhdl();
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} else {
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$self->_read_inputs_v();
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}
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my $filename = $self->{main_filename};
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my $fh = IO::File->new(">$filename") or die "%Error: $! $filename,";
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@ -959,8 +1030,17 @@ sub _print_advance_time {
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sub _make_top {
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my $self = shift;
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if ($self->vhdl) {
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$self->_make_top_vhdl;
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} else {
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$self->_make_top_v;
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}
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}
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$self->_read_inputs();
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sub _make_top_v {
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my $self = shift;
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$self->_read_inputs_v();
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my $fh = IO::File->new(">$self->{top_shell_filename}") or die "%Error: $! $self->{top_shell_filename},";
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print $fh "module top;\n";
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@ -1007,6 +1087,61 @@ sub _make_top {
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$fh->close();
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}
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sub _make_top_vhdl {
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my $self = shift;
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$self->_read_inputs_vhdl();
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my $fh = IO::File->new(">$self->{top_shell_filename}") or die "%Error: $! $self->{top_shell_filename},";
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print $fh "library ieee;\n";
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my @ports = sort (keys %{$self->{inputs}});
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print $fh "entity t_ent is\n";
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if ($#ports >= 0) {
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print $fh " port(\n";
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my $semi = "";
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foreach my $inp (@ports) {
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print $fh "\t${semi}${inp} : in std_logic\n";
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$semi=";";
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}
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print $fh " );\n";
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}
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print $fh "end;\n";
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print $fh "entity top is\n";
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print $fh "end;\n";
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# Inst
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print $fh "architecture t_beh of t_ent is\n";
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if ($#ports >= 0) {
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foreach my $inp (@ports) {
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print $fh "\tsignal ${inp} : std_logic := '0';\n";
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}
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}
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print $fh " begin\n";
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print $fh " t : t_ent\n";
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if ($#ports >= 0) {
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print $fh " port map(\n";
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my $comma="";
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foreach my $inp (@ports) {
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print $fh "\t${comma}${inp} => ${inp}\n";
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$comma=",";
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}
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print $fh " )\n";
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}
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print $fh " ;\n";
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print $fh " end;\n";
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# Waves TBD
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# Test TBD
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print $fh "end;\n";
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$fh->close();
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}
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#######################################################################
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sub _sp_preproc {
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@ -1025,7 +1160,7 @@ sub _sp_preproc {
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#######################################################################
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sub _read_inputs {
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sub _read_inputs_v {
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my $self = shift;
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my $filename = $self->{top_filename};
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$filename = "$self->{t_dir}/$filename" if !-r $filename;
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@ -1041,6 +1176,27 @@ sub _read_inputs {
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$fh->close();
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}
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#######################################################################
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sub _read_inputs_vhdl {
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my $self = shift;
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my $filename = $self->{top_filename};
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$filename = "$self->{t_dir}/$filename" if !-r $filename;
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my $fh = IO::File->new("<$filename") or die "%Error: $! $filename,";
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while (defined(my $line = $fh->getline)) {
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# Only supports this form right now:
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# signal: in ...
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# signal: out ...
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if ($line =~ /^\s*(\S+)\s*:\s*(in)\b\s*/) {
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$self->{inputs}{$1} = $1;
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}
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if ($line =~ /^\s*(architecture)/) {
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last;
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}
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}
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$fh->close();
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}
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#######################################################################
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# Verilator utilities
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@ -1277,6 +1433,10 @@ Requires --debug.
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Run Verilator generated executable under the debugger.
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=item --ghdl
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Run using GHDL.
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=item --golden
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Update golden files, equivalent to setting HARNESS_UPDATE_GOLDEN=1.
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@ -1329,6 +1489,10 @@ Run using Verilator.
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Root directory name of SystemC kit.
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=item VERILATOR_GHDL
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Command to use to invoke GHDL.
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=item VERILATOR_IVERILOG
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Command to use to invoke Icarus Verilog.
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