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Tests: $countbits
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@ -56,6 +56,8 @@ module t(/*AUTOARG*/
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result_70_3 = $countbits(in70, ctrl0, ctrl1, ctrl2);
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end
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logic [31:0] val = 32'h70008421;
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integer cyc=0;
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// Test loop
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always @ (posedge clk) begin
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@ -70,6 +72,14 @@ module t(/*AUTOARG*/
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if ($countbits(20'b1100x01z101, 2, 2'bx1) != 18) $stop;
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if ($countbits(32'b1100x01z101, 'x, 'z) != 2) $stop;
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if ($countbits(32'b1100x01z101, 'x, 'z, '1) != 7) $stop;
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`ifndef VERILATOR // Unsup
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if ($countbits(val, '1) != 7) $stop;
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if ($countones(val) != 7) $stop;
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if ($countbits(val, '0) != 25) $stop;
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if ($countbits(val, '0, '1) != 32) $stop;
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if ($countbits(val, 'x, 'z) != 0) $stop;
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`endif
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end
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else if (cyc == 1) begin
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in16 <= 16'h0AF0;
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