Fix dumping waveforms to multiple FST files (#2889)

docs/CONTRIBUTORS

@@ -11,6 +11,7 @@ Chris Randall
 Conor McCullough
 Dan Petrisko
 David Horton
+David Metz
 David Stanford
 David Turner
 Drew Taussig

include/verilated_fst_c.cpp

@@ -105,6 +105,7 @@ void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
 #ifdef VL_TRACE_FST_WRITER_THREAD
     fstWriterSetParallelMode(m_fst, 1);
 #endif
+    fullDump(true);  // First dump must be full for fst
 
     m_curScope.clear();
 

test_regress/t/t_trace_cat_fst.cpp

@@ -0,0 +1,54 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2008 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+#include <memory>
+#include <verilated.h>
+#include <verilated_fst_c.h>
+
+#include VM_PREFIX_INCLUDE
+
+unsigned long long main_time = 0;
+double sc_time_stamp() { return (double)main_time; }
+
+const char* trace_name() {
+    static char name[1000];
+    VL_SNPRINTF(name, 1000, VL_STRINGIFY(TEST_OBJ_DIR) "/simpart_%04d.fst", (int)main_time);
+    return name;
+}
+
+int main(int argc, char** argv, char** env) {
+    std::unique_ptr<VM_PREFIX> top{new VM_PREFIX("top")};
+
+    Verilated::debug(0);
+    Verilated::traceEverOn(true);
+
+    std::unique_ptr<VerilatedFstC> tfp{new VerilatedFstC};
+    top->trace(tfp.get(), 99);
+
+    tfp->open(trace_name());
+
+    top->clk = 0;
+
+    while (main_time < 190) {  // Creates 2 files
+        top->clk = !top->clk;
+        top->eval();
+
+        if ((main_time % 100) == 0) {
+            tfp->close();
+            tfp->open(trace_name());
+        }
+        tfp->dump((unsigned int)(main_time));
+        ++main_time;
+    }
+    tfp->close();
+    top->final();
+    tfp.reset();
+    top.reset();
+    printf("*-* All Finished *-*\n");
+    return 0;
+}

test_regress/t/t_trace_cat_fst.pl

@@ -0,0 +1,29 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2013 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt_all => 1);
+
+compile(
+    make_top_shell => 0,
+    make_main => 0,
+    v_flags2 => ["--trace-fst --exe $Self->{t_dir}/t_trace_cat_fst.cpp"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+fst_identical("$Self->{obj_dir}/simpart_0000.fst",
+              "t/$Self->{name}_0000.out");
+fst_identical("$Self->{obj_dir}/simpart_0100.fst",
+              "t/$Self->{name}_0100.out");
+
+ok(1);
+1;

test_regress/t/t_trace_cat_fst.v

@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2013 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t
+  (
+   input wire clk
+   );
+
+   integer    cyc; initial cyc = 0;
+   integer    unchanged; initial unchanged = 42;
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+   end
+endmodule

test_regress/t/t_trace_cat_fst_0000.out

@@ -0,0 +1,272 @@
+$date
+	Wed Apr 14 17:11:07 2021
+
+$end
+$version
+	fstWriter
+$end
+$timescale
+	1ps
+$end
+$scope module top $end
+$var wire 1 ! clk $end
+$scope module t $end
+$var wire 1 ! clk $end
+$var integer 32 " cyc $end
+$var integer 32 # unchanged $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b00000000000000000000000000101010 #
+b00000000000000000000000000000000 "
+1!
+$end
+#1
+0!
+#2
+1!
+b00000000000000000000000000000001 "
+#3
+0!
+#4
+1!
+b00000000000000000000000000000010 "
+#5
+0!
+#6
+1!
+b00000000000000000000000000000011 "
+#7
+0!
+#8
+1!
+b00000000000000000000000000000100 "
+#9
+0!
+#10
+1!
+b00000000000000000000000000000101 "
+#11
+0!
+#12
+1!
+b00000000000000000000000000000110 "
+#13
+0!
+#14
+1!
+b00000000000000000000000000000111 "
+#15
+0!
+#16
+1!
+b00000000000000000000000000001000 "
+#17
+0!
+#18
+1!
+b00000000000000000000000000001001 "
+#19
+0!
+#20
+1!
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+#21
+0!
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+1!
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+#23
+0!
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+1!
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+#25
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+1!
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+1!
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+1!
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+#37
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+1!
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+#39
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+1!
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+#41
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+1!
+b00000000000000000000000000010101 "
+#43
+0!
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+1!
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+#45
+0!
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+1!
+b00000000000000000000000000010111 "
+#47
+0!
+#48
+1!
+b00000000000000000000000000011000 "
+#49
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+1!
+b00000000000000000000000000011001 "
+#51
+0!
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+1!
+b00000000000000000000000000011010 "
+#53
+0!
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+1!
+b00000000000000000000000000011011 "
+#55
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+#56
+1!
+b00000000000000000000000000011100 "
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+1!
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+1!
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+1!
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+1!
+b00000000000000000000000000101000 "
+#81
+0!
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+1!
+b00000000000000000000000000101001 "
+#83
+0!
+#84
+1!
+b00000000000000000000000000101010 "
+#85
+0!
+#86
+1!
+b00000000000000000000000000101011 "
+#87
+0!
+#88
+1!
+b00000000000000000000000000101100 "
+#89
+0!
+#90
+1!
+b00000000000000000000000000101101 "
+#91
+0!
+#92
+1!
+b00000000000000000000000000101110 "
+#93
+0!
+#94
+1!
+b00000000000000000000000000101111 "
+#95
+0!
+#96
+1!
+b00000000000000000000000000110000 "
+#97
+0!
+#98
+1!
+b00000000000000000000000000110001 "
+#99
+0!

test_regress/t/t_trace_cat_fst_0100.out

@@ -0,0 +1,247 @@
+$date
+	Wed Apr 14 17:04:26 2021
+
+$end
+$version
+	fstWriter
+$end
+$timescale
+	1ps
+$end
+$scope module top $end
+$var wire 1 ! clk $end
+$scope module t $end
+$var wire 1 ! clk $end
+$var integer 32 " cyc $end
+$var integer 32 # unchanged $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#100
+$dumpvars
+b00000000000000000000000000101010 #
+b00000000000000000000000000110010 "
+1!
+$end
+#101
+0!
+#102
+1!
+b00000000000000000000000000110011 "
+#103
+0!
+#104
+1!
+b00000000000000000000000000110100 "
+#105
+0!
+#106
+1!
+b00000000000000000000000000110101 "
+#107
+0!
+#108
+1!
+b00000000000000000000000000110110 "
+#109
+0!
+#110
+1!
+b00000000000000000000000000110111 "
+#111
+0!
+#112
+1!
+b00000000000000000000000000111000 "
+#113
+0!
+#114
+1!
+b00000000000000000000000000111001 "
+#115
+0!
+#116
+1!
+b00000000000000000000000000111010 "
+#117
+0!
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+1!
+b00000000000000000000000000111011 "
+#119
+0!
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+1!
+b00000000000000000000000000111100 "
+#121
+0!
+#122
+1!
+b00000000000000000000000000111101 "
+#123
+0!
+#124
+1!
+b00000000000000000000000000111110 "
+#125
+0!
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+1!
+b00000000000000000000000000111111 "
+#127
+0!
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+1!
+b00000000000000000000000001000000 "
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+0!
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+1!
+b00000000000000000000000001001011 "
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+1!
+b00000000000000000000000001001100 "
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+1!
+b00000000000000000000000001001101 "
+#155
+0!
+#156
+1!
+b00000000000000000000000001001110 "
+#157
+0!
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+1!
+b00000000000000000000000001001111 "
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+1!
+b00000000000000000000000001010000 "
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+0!
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+1!
+b00000000000000000000000001010001 "
+#163
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+1!
+b00000000000000000000000001010010 "
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+1!
+b00000000000000000000000001010011 "
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+0!
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+1!
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+b00000000000000000000000001011001 "
+#179
+0!
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+1!
+b00000000000000000000000001011010 "
+#181
+0!
+#182
+1!
+b00000000000000000000000001011011 "
+#183
+0!
+#184
+1!
+b00000000000000000000000001011100 "
+#185
+0!
+#186
+1!
+b00000000000000000000000001011101 "
+#187
+0!
+#188
+1!
+b00000000000000000000000001011110 "
+#189
+0!