diff --git a/test_regress/t/t_bitsel_const_bad.pl b/test_regress/t/t_bitsel_const_bad.pl
new file mode 100755
index 000000000..992015386
--- /dev/null
+++ b/test_regress/t/t_bitsel_const_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+'%Error: t/t_bitsel_const_bad.v:\d+: Illegal bit or array select; variable already selected, or bad dimension: b
+.*
+%Error: Exiting due to.*',
+	 );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_bitsel_const_bad.v b/test_regress/t/t_bitsel_const_bad.v
new file mode 100644
index 000000000..918ba6ffe
--- /dev/null
+++ b/test_regress/t/t_bitsel_const_bad.v
@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Test of select from constant
+//
+// This tests issue 508, bit select of constant fails
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Jeremy Bennett.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   // Note that if we declare "wire [0:0] b", this works just fine.
+   wire  a;
+   wire  b;
+
+   assign b = 1'b0;
+   assign a = b[0];  // IEEE illegal can't extract scalar
+
+endmodule
diff --git a/test_regress/t/t_bitsel_wire_array_bad.pl b/test_regress/t/t_bitsel_wire_array_bad.pl
new file mode 100755
index 000000000..b2b725f30
--- /dev/null
+++ b/test_regress/t/t_bitsel_wire_array_bad.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+# Comple time only test
+
+compile (
+	 verilator_flags2 => ["--lint-only"],
+	 fails=>1,
+#	 expect=>
+# TBD better error message, bug509
+#'.*
+#%Error: Exiting due to.*',
+	 );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_bitsel_wire_array_bad.v b/test_regress/t/t_bitsel_wire_array_bad.v
new file mode 100644
index 000000000..90c050162
--- /dev/null
+++ b/test_regress/t/t_bitsel_wire_array_bad.v
@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Test of select from constant
+//
+// This tests issue 509, bit select of constant fails
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Jeremy Bennett.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   // a and b are arrays of length 1.
+   wire  a[0:0];  // Array of nets
+   wire  b[0:0];
+
+   assign a = 1'b0;  // Only net assignment allowed
+   assign b = a[0];  // Only net assignment allowed
+
+endmodule