From f435d9624180c6b0d511f427ff41a876e3c7aaea Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 15 Aug 2022 21:56:09 -0400
Subject: [PATCH] Fix case statement comparing string literal (#3544).

---
 Changes                          |  1 +
 src/V3Width.cpp                  |  4 +++-
 test_regress/t/t_case_string2.pl | 21 +++++++++++++++++++++
 test_regress/t/t_case_string2.v  | 21 +++++++++++++++++++++
 4 files changed, 46 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_case_string2.pl
 create mode 100644 test_regress/t/t_case_string2.v

diff --git a/Changes b/Changes
index ba347daf3..65ee0fd39 100644
--- a/Changes
+++ b/Changes
@@ -19,6 +19,7 @@ Verilator 4.225 devel
 * Fix wrong bit op tree optimization (#3509). [Nathan Graybeal]
 * Fix incorrect tristate logic (#3399) [shareefj, Vighnesh Iyer]
 * Fix segfault exporting non-existant package (#3535).
+* Fix case statement comparing string literal (#3544). [Gustav Svensk]
 
 
 Verilator 4.224 2022-06-19
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 91de05a95..824d66beb 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3977,8 +3977,10 @@ private:
              itemp = VN_AS(itemp->nextp(), CaseItem)) {
             for (AstNode* condp = itemp->condsp(); condp; condp = condp->nextp()) {
                 if (condp->dtypep() != subDTypep) {
-                    if (condp->dtypep()->isDouble()) {
+                    if (condp->dtypep()->isDouble() || subDTypep->isDouble()) {
                         subDTypep = nodep->findDoubleDType();
+                    } else if (condp->dtypep()->isString() || subDTypep->isString()) {
+                        subDTypep = nodep->findStringDType();
                     } else {
                         const int width = std::max(subDTypep->width(), condp->width());
                         const int mwidth = std::max(subDTypep->widthMin(), condp->widthMin());
diff --git a/test_regress/t/t_case_string2.pl b/test_regress/t/t_case_string2.pl
new file mode 100755
index 000000000..1aa73f80a
--- /dev/null
+++ b/test_regress/t/t_case_string2.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_case_string2.v b/test_regress/t/t_case_string2.v
new file mode 100644
index 000000000..f2722639b
--- /dev/null
+++ b/test_regress/t/t_case_string2.v
@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+function automatic string broken_case(input string some_string);
+    case(some_string)
+        "alpha": return "alpha";
+        default: return "beta";
+    endcase
+endfunction
+
+   initial begin
+      $display(broken_case("gamma"));
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule