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https://github.com/verilator/verilator.git
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parent
2a905c1d6e
commit
f3cc32554c
@ -427,7 +427,8 @@ AstNode* V3Begin::convertToWhile(AstForeach* nodep) {
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AstNode* bodyPointp = new AstBegin{nodep->fileline(), "[EditWrapper]", nullptr};
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AstNode* bodyPointp = new AstBegin{nodep->fileline(), "[EditWrapper]", nullptr};
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AstNode* newp = nullptr;
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AstNode* newp = nullptr;
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AstNode* lastp = nodep;
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AstNode* lastp = nodep;
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// subfromp used to traverse each dimension of multi-d queue/dyn-arr's
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AstNodeExpr* subfromp = fromp->cloneTreePure(false);
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// Major dimension first
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// Major dimension first
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for (AstNode *argsp = loopsp->elementsp(), *next_argsp; argsp; argsp = next_argsp) {
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for (AstNode *argsp = loopsp->elementsp(), *next_argsp; argsp; argsp = next_argsp) {
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next_argsp = argsp->nextp();
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next_argsp = argsp->nextp();
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@ -458,7 +459,10 @@ AstNode* V3Begin::convertToWhile(AstForeach* nodep) {
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} else if (VN_IS(fromDtp, DynArrayDType) || VN_IS(fromDtp, QueueDType)) {
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} else if (VN_IS(fromDtp, DynArrayDType) || VN_IS(fromDtp, QueueDType)) {
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AstConst* const leftp = new AstConst{fl, 0};
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AstConst* const leftp = new AstConst{fl, 0};
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AstNodeExpr* const rightp
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AstNodeExpr* const rightp
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= new AstCMethodHard{fl, fromp->cloneTreePure(false), "size"};
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= new AstCMethodHard{fl, subfromp->cloneTreePure(false), "size"};
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AstVarRef* varRefp = new AstVarRef{fl, varp, VAccess::READ};
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subfromp = new AstCMethodHard{fl, subfromp, "at", varRefp};
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subfromp->dtypep(fromDtp);
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rightp->dtypeSetSigned32();
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rightp->dtypeSetSigned32();
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rightp->protect(false);
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rightp->protect(false);
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loopp = createForeachLoop(nodep, bodyPointp, varp, leftp, rightp, VNType::atLt);
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loopp = createForeachLoop(nodep, bodyPointp, varp, leftp, rightp, VNType::atLt);
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18
test_regress/t/t_foreach_array.py
Executable file
18
test_regress/t/t_foreach_array.py
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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74
test_regress/t/t_foreach_array.v
Executable file
74
test_regress/t/t_foreach_array.v
Executable file
@ -0,0 +1,74 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by PlanV GmbH.
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// SPDX-License-Identifier: CC0-1.0
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module t_foreach_array;
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int dyn_arr[][];
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int queue[$][$];
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int unpacked_arr [3:1][9:8];
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int count_que;
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int exp_count_que;
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int count_dyn;
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int exp_count_dyn;
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int count_unp;
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int exp_count_unp;
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initial begin
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// Initialize
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queue = '{'{1, 2, 3}, '{4, 5}, '{6}};
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dyn_arr = '{'{1, 2, 3}, '{4, 5, 6, 0, 10}, '{6, 7, 8, 9}};
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count_que = 0;
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foreach(queue[i, j]) begin
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count_que++;
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end
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exp_count_que = 0;
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foreach(queue[i]) begin
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foreach(queue[i][j]) begin
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exp_count_que++;
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end
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end
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count_dyn = 0;
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foreach(dyn_arr[i, j]) begin
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count_dyn++;
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end
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exp_count_dyn = 0;
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foreach(dyn_arr[i]) begin
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foreach(dyn_arr[i][j]) begin
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exp_count_dyn++;
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end
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end
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count_unp = 0;
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foreach(unpacked_arr[i, j]) begin
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count_unp++;
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end
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exp_count_unp = 0;
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foreach(unpacked_arr[i]) begin
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foreach(unpacked_arr[i][j]) begin
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exp_count_unp++;
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end
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end
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if (count_que != 6 || count_que != exp_count_que) $stop;
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if (count_dyn != 12 || count_dyn != exp_count_dyn) $stop;
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if (count_unp != 6 || count_unp != exp_count_unp) $stop;
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$write("*-* All Finished *-*\\n");
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$finish;
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end
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endmodule
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