diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp
index 56dc57067..a84bef91b 100644
--- a/src/V3WidthSel.cpp
+++ b/src/V3WidthSel.cpp
@@ -352,7 +352,9 @@ private:
 	FromData fromdata = fromDataForArray(nodep, fromp, width!=1);
 	AstNodeDType* ddtypep = fromdata.m_dtypep;
 	VNumRange fromRange = fromdata.m_fromRange;
-	if (ddtypep->castBasicDType()) {
+	if (ddtypep->castBasicDType()
+	    || (ddtypep->castNodeClassDType()
+		&& ddtypep->castNodeClassDType()->packed())) {
 	    AstSel* newp = NULL;
 	    if (nodep->castSelPlus()) {
 		if (fromRange.littleEndian()) {
diff --git a/test_regress/t/t_bitsel_struct3.pl b/test_regress/t/t_bitsel_struct3.pl
new file mode 100755
index 000000000..f91289753
--- /dev/null
+++ b/test_regress/t/t_bitsel_struct3.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_bitsel_struct3.v b/test_regress/t/t_bitsel_struct3.v
new file mode 100644
index 000000000..1c10278e8
--- /dev/null
+++ b/test_regress/t/t_bitsel_struct3.v
@@ -0,0 +1,42 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// A test case for struct signal bit selection.
+//
+// This test is to check that bit selection of multi-dimensional signal inside
+// of a packed struct works. Currently +: and -: blow up with packed structs.
+//
+// This file ONLY is placed into the Public Domain, for any use, without
+// warranty, 2013 by Jie Xu.
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   typedef struct packed {
+       logic [15:0] channel;
+       logic [15:0] others;
+   } buss_t;
+
+   buss_t     b;
+
+   reg [7:0]  a;
+   reg [7:0]  c;
+   reg [7:0]  d;
+
+   initial begin
+      b = {16'h8765,16'h4321};
+      a = b[19:12];			// This works
+      c = b[8+:8];			// This fails
+      d = b[11-:8];			// This fails
+      if ((a == 8'h54) && (c == 8'h43) && (d == 8'h32)) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+      else begin
+	 $stop;
+      end
+   end
+
+endmodule