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Fix --comp-limit-parens with real data types
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@ -53,14 +53,8 @@ private:
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// if (debug() >= 9) nodep->dumpTree(cout, "deep:");
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string newvarname = (string("__Vdeeptemp") + cvtToStr(m_modp->varNumGetInc()));
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AstVar* varp = new AstVar(nodep->fileline(), AstVarType::STMTTEMP, newvarname,
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// Width, not widthMin, as we may be in
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// middle of BITSEL expression which though
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// it's one bit wide, needs the mask in the
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// upper bits. (Someday we'll have a valid
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// bitmask instead of widths....)
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// See t_func_crc for an example test that requires this
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VFlagLogicPacked(), nodep->width());
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AstVar* varp
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= new AstVar(nodep->fileline(), AstVarType::STMTTEMP, newvarname, nodep->dtypep());
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UASSERT_OBJ(m_cfuncp, nodep, "Deep expression not under a function");
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m_cfuncp->addInitsp(varp);
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// Replace node tree with reference to var
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24
test_regress/t/t_flag_comp_limit_parens.pl
Executable file
24
test_regress/t/t_flag_comp_limit_parens.pl
Executable file
@ -0,0 +1,24 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2008 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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compile(
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verilator_flags2 => ["--comp-limit-parens 2"],
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);
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execute(
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check_finished => 1,
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);
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file_grep("$Self->{obj_dir}/Vt_flag_comp_limit_parens__Slow.cpp", qr/Vdeeptemp/x);
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ok(1);
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1;
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19
test_regress/t/t_flag_comp_limit_parens.v
Normal file
19
test_regress/t/t_flag_comp_limit_parens.v
Normal file
@ -0,0 +1,19 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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r
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);
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input real r;
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initial begin
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$display("%g", $cos($cos($cos($cos($cos($cos($cos($cos(r + 0.1)))))))));
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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