Fix --comp-limit-parens with real data types

This commit is contained in:
Wilson Snyder 2021-03-28 20:18:18 -04:00
parent 2ca21c01d2
commit f26a7c2a5d
3 changed files with 45 additions and 8 deletions

View File

@ -53,14 +53,8 @@ private:
// if (debug() >= 9) nodep->dumpTree(cout, "deep:");
string newvarname = (string("__Vdeeptemp") + cvtToStr(m_modp->varNumGetInc()));
AstVar* varp = new AstVar(nodep->fileline(), AstVarType::STMTTEMP, newvarname,
// Width, not widthMin, as we may be in
// middle of BITSEL expression which though
// it's one bit wide, needs the mask in the
// upper bits. (Someday we'll have a valid
// bitmask instead of widths....)
// See t_func_crc for an example test that requires this
VFlagLogicPacked(), nodep->width());
AstVar* varp
= new AstVar(nodep->fileline(), AstVarType::STMTTEMP, newvarname, nodep->dtypep());
UASSERT_OBJ(m_cfuncp, nodep, "Deep expression not under a function");
m_cfuncp->addInitsp(varp);
// Replace node tree with reference to var

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@ -0,0 +1,24 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2008 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
compile(
verilator_flags2 => ["--comp-limit-parens 2"],
);
execute(
check_finished => 1,
);
file_grep("$Self->{obj_dir}/Vt_flag_comp_limit_parens__Slow.cpp", qr/Vdeeptemp/x);
ok(1);
1;

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@ -0,0 +1,19 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
r
);
input real r;
initial begin
$display("%g", $cos($cos($cos($cos($cos($cos($cos($cos(r + 0.1)))))))));
$write("*-* All Finished *-*\n");
$finish;
end
endmodule