diff --git a/Changes b/Changes index f2e5e629d..87a44340a 100644 --- a/Changes +++ b/Changes @@ -39,6 +39,7 @@ Verilator 5.025 devel * Fix macro expansion in strings per 1800-2023 (#5094). [Geza Lore] * Fix width extension of unpacked array select (#5095). [Varun Koyyalagunta] * Fix MacOS missing header (#5096) (#5097). [Vito Gamberini] +* Fix tracing interface functions (#5108). [Alex Solomatnikov] Verilator 5.024 2024-04-05 diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp index d46d97e9b..ec02f71a0 100644 --- a/src/V3TraceDecl.cpp +++ b/src/V3TraceDecl.cpp @@ -313,7 +313,7 @@ class TraceDeclVisitor final : public VNVisitor { for (AstCFunc* const funcp : pair.second) { AstNode* prevp = nullptr; AstNode* currp = funcp->stmtsp(); - while (true) { + while (currp) { AstNode* const nextp = currp->nextp(); if (VN_IS(prevp, TracePushPrefix) && VN_IS(currp, TracePopPrefix)) { VL_DO_DANGLING(prevp->unlinkFrBack()->deleteTree(), prevp); diff --git a/test_regress/t/t_trace_iface.out b/test_regress/t/t_trace_iface.out new file mode 100644 index 000000000..3cf7ce8da --- /dev/null +++ b/test_regress/t/t_trace_iface.out @@ -0,0 +1,136 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $var wire 1 ( clk $end + $scope module t $end + $var wire 1 ( clk $end + $var wire 32 # cyc [31:0] $end + $scope module c5_data $end + $var wire 1 $ valid $end + $var wire 4 % value [3:0] $end + $var wire 1 ) reset $end + $upscope $end + $scope module c6_data $end + $var wire 1 & valid $end + $var wire 4 ' value [3:0] $end + $var wire 1 * reset $end + $upscope $end + $scope module cif2 $end + $upscope $end + $scope module cif3 $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000001 # +0$ +b0000 % +0& +b0000 ' +0( +0) +0* +#10 +b00000000000000000000000000000010 # +1( +#15 +0( +#20 +b00000000000000000000000000000011 # +b1111 % +1& +b1010 ' +1( +#25 +0( +#30 +b00000000000000000000000000000100 # +1( +#35 +0( +#40 +b00000000000000000000000000000101 # +1( +#45 +0( +#50 +b00000000000000000000000000000110 # +1( +#55 +0( +#60 +b00000000000000000000000000000111 # +1( +#65 +0( +#70 +b00000000000000000000000000001000 # +1( +#75 +0( +#80 +b00000000000000000000000000001001 # +1( +#85 +0( +#90 +b00000000000000000000000000001010 # +1( +#95 +0( +#100 +b00000000000000000000000000001011 # +1( +#105 +0( +#110 +b00000000000000000000000000001100 # +1( +#115 +0( +#120 +b00000000000000000000000000001101 # +1( +#125 +0( +#130 +b00000000000000000000000000001110 # +1( +#135 +0( +#140 +b00000000000000000000000000001111 # +1( +#145 +0( +#150 +b00000000000000000000000000010000 # +1( +#155 +0( +#160 +b00000000000000000000000000010001 # +1( +#165 +0( +#170 +b00000000000000000000000000010010 # +1( +#175 +0( +#180 +b00000000000000000000000000010011 # +1( +#185 +0( +#190 +b00000000000000000000000000010100 # +1( +#195 +0( +#200 +b00000000000000000000000000010101 # +1( diff --git a/test_regress/t/t_trace_iface.pl b/test_regress/t/t_trace_iface.pl new file mode 100755 index 000000000..a17d59021 --- /dev/null +++ b/test_regress/t/t_trace_iface.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +compile( + verilator_flags2 => ['--trace'], + ); + +execute( + check_finished => 1, + ); + +vcd_identical($Self->trace_filename, $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_trace_iface.v b/test_regress/t/t_trace_iface.v new file mode 100644 index 000000000..eeb87f509 --- /dev/null +++ b/test_regress/t/t_trace_iface.v @@ -0,0 +1,77 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +interface counter_if; + logic valid; + logic [3:0] value; + logic reset; + modport counter_mp (input reset, output valid, output value); + modport core_mp (output reset, input valid, input value); +endinterface + +interface counter_if2 (counter_if.counter_mp c_mp); + task automatic reset(); + c_mp.valid = '0; + c_mp.value = '0; + endtask + task automatic init(); + c_mp.valid = '0; + c_mp.value = '1; + endtask +endinterface + +interface counter_if3 (counter_if.counter_mp c_mp); + task automatic reset(); + c_mp.valid = '0; + c_mp.value = '0; + endtask + task automatic init(); + c_mp.valid = '1; + c_mp.value = 4'ha; + endtask +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + counter_if c5_data(); + counter_if c6_data(); + + counter_if2 cif2(c5_data.counter_mp); + counter_if3 cif3(c6_data.counter_mp); + + initial begin + cif2.reset(); + cif3.reset(); + end + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc<2) begin + if (c5_data.valid != '0) $stop; + if (c5_data.value != '0) $stop; + if (c6_data.valid != '0) $stop; + if (c6_data.value != '0) $stop; + end + if (cyc==2) begin + cif2.init(); + cif3.init(); + end + if (cyc==20) begin + if (c5_data.valid != '0) $stop; + if (c5_data.value != '1) $stop; + if (c6_data.valid != '1) $stop; + if (c6_data.value != 10) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule