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Add error message when modules have duplicate names.

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@1025 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2008-04-09 13:56:40 +00:00
parent 3a2f8224e4
commit ecdbd72fa1
4 changed files with 48 additions and 1 deletions
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4
Changes
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@ -3,6 +3,10 @@ Revision history for Verilator
The contributors that suggested a given feature are shown in []. [by ...]
indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.66***
**** Add error message when modules have duplicate names. [Stefan Thiede]
* Verilator 3.661 2008/04/04
*** The --enable-defenv configure option added in 3.660 is now the default.

6
src/V3LinkCells.cpp
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@ -210,7 +210,11 @@ private:
void readModNames() {
// Look at all modules, and store pointers to all module names
for (AstModule* nodep = v3Global.rootp()->modulesp(); nodep; nodep=nodep->nextp()->castModule()) {
if (!m_mods.findIdName(nodep->name())) {
AstNode* foundp = m_mods.findIdName(nodep->name());
if (foundp && foundp != nodep) {
nodep->v3error("Duplicate declaration of module: "<<nodep->prettyName());
foundp->v3error("... Location of original declaration");
} else if (!foundp) {
m_mods.insert(nodep->name(), nodep);
}
}

21
test_regress/t/t_mod_dup_bad.pl Executable file
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@ -0,0 +1,21 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2008 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
compile (
fails=>$Last_Self->{v3},
nc=>0, # Need to get it not to give the prompt
expect=>
'%Error: t/t_mod_dup_bad.v:\d+: Duplicate declaration of module: a
%Error: t/t_mod_dup_bad.v:\d+: ... Location of original declaration
.*
%Error: Exiting due to.*',
) if $Last_Self->{v3};
ok(1);
1;

18
test_regress/t/t_mod_dup_bad.v Normal file
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@ -0,0 +1,18 @@
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module a();
endmodule
module test();
a a();
endmodule
module a();
endmodule
module b();
endmodule