diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h
index df32e9455..3dc9d7d2c 100644
--- a/src/V3AstNodeDType.h
+++ b/src/V3AstNodeDType.h
@@ -209,6 +209,12 @@ protected:
         m_packed = (numericUnpack != VSigning::NOSIGN);
         numeric(VSigning::fromBool(numericUnpack.isSigned()));
     }
+    AstNodeUOrStructDType(const AstNodeUOrStructDType& other)
+        : AstNodeDType(other)
+        , m_name(other.m_name)
+        , m_uniqueNum(uniqueNumInc())
+        , m_packed(other.m_packed)
+        , m_isFourstate(other.m_isFourstate) {}
 
 public:
     ASTGEN_MEMBERS_AstNodeUOrStructDType;
@@ -664,6 +670,11 @@ public:
         childDTypep(dtp);  // Only for parser
         dtypep(nullptr);  // V3Width will resolve
     }
+    AstDefImplicitDType(const AstDefImplicitDType& other)
+        : AstNodeDType(other)
+        , m_name(other.m_name)
+        , m_containerp(other.m_containerp)
+        , m_uniqueNum(uniqueNumInc()) {}
     ASTGEN_MEMBERS_AstDefImplicitDType;
     int uniqueNum() const { return m_uniqueNum; }
     bool same(const AstNode* samep) const override {
@@ -793,6 +804,10 @@ public:
         dtypep(nullptr);  // V3Width will resolve
         widthFromSub(subDTypep());
     }
+    AstEnumDType(const AstEnumDType& other)
+        : AstNodeDType(other)
+        , m_name(other.m_name)
+        , m_uniqueNum(uniqueNumInc()) {}
     ASTGEN_MEMBERS_AstEnumDType;
 
     const char* broken() const override;
diff --git a/test_regress/t/t_enum_name_sformatf.py b/test_regress/t/t_enum_name_sformatf.py
new file mode 100755
index 000000000..d4f986441
--- /dev/null
+++ b/test_regress/t/t_enum_name_sformatf.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_enum_name_sformatf.v b/test_regress/t/t_enum_name_sformatf.v
new file mode 100644
index 000000000..f629d1896
--- /dev/null
+++ b/test_regress/t/t_enum_name_sformatf.v
@@ -0,0 +1,35 @@
+// DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module sub #(parameter int param_a, parameter bit [1:0] enum_param = '0) ();
+   typedef enum logic [1:0] {
+       FOO = enum_param,
+       BAR,
+       BAZ
+   } enum_t;
+   enum_t the_enum = enum_t'(1);
+
+   initial $display("%s", the_enum.name());
+endmodule
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   // finish report
+   always @ (posedge clk) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+   sub #(.param_a(1)) the_sub1();
+   sub #(.param_a(2)) the_sub2();
+   sub #(.param_a(2), .enum_param(2'd1)) the_sub3();
+
+endmodule