Move test_v submodule into t_case_orig. No functional change

test_regress/t/t_case_orig.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_case_orig.v

@@ -3,17 +3,12 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2003 by Wilson Snyder.
 
-`include "verilated.v"
-
-module t_case(/*AUTOARG*/
-   // Outputs
-   passed,
+module t (/*AUTOARG*/
    // Inputs
    clk
    );
 
    input clk;
-   output passed;  reg passed; initial passed = 0;
    reg 	 _ranit;
 
    reg 	 rnd;
@@ -111,17 +106,11 @@ module t_case(/*AUTOARG*/
 	 //
 
 	 if (rnd) begin
-	    // This gets covered
-	    $write("");
-	 end
-	 if (rnd) begin
-	    // This doesn't
-	    // verilator coverage_block_off
 	    $write("");
 	 end
 	 //
-	 $write("[%0t] t_case: Passed\n", $time);
-	 passed <= 1'b1;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
       end
    end
 

test_v/t.v

@@ -26,11 +26,7 @@ module t (/*AUTOARG*/
       /*AUTOINST*/
       // Inputs
       .clk				(clk));
-   t_case  tcase
-     (.passed		(passedv[1]),
-      /*AUTOINST*/
-      // Inputs
-      .clk				(clk));
+   assign passedv[1] = 1'b1;
    assign passedv[2] = 1'b1;
    assign passedv[3] = 1'b1;
    assign passedv[4] = 1'b1;