Add --no-trace-top option (#4422)

bin/verilator

@@ -440,6 +440,7 @@ detailed descriptions of these arguments.
     --trace-params              Enable tracing of parameters
     --trace-structs             Enable tracing structure names
     --trace-threads <threads>   Enable FST waveform creation on separate threads
+    --no-trace-top              Do not emit traces for signals in the top module generated by verilator
     --trace-underscore          Enable tracing of _signals
      -U<var>                    Undefine preprocessor define
     --no-unlimited-stack        Don't disable stack size limit

docs/CONTRIBUTORS

@@ -40,6 +40,7 @@ Fan Shupei
 february cozzocrea
 Felix Neumärker
 Felix Yan
+Frans Skarman
 G-A. Kamendje
 Garrett Smith
 Geza Lore

docs/guide/exe_verilator.rst

@@ -1314,6 +1314,7 @@ Summary:
    This is not needed with standard designs with only one top.  See also
    :option:`MULTITOP` warning.
 
+
 .. option:: --trace
 
    Adds waveform tracing code to the model using VCD format. This overrides
@@ -1392,6 +1393,17 @@ Summary:
    This option is accepted, but has absolutely no effect with
    :vlopt:`--trace`, which respects :vlopt:`--threads` instead.
 
+.. option:: --no-trace-top
+
+   Disables tracing for the input and output signals in the top wrapper which
+   Verilator adds to the design. The signals are still traced in the original
+   verilog top modules.
+
+   When combined with :option:`--main-top-name` set to "-" or when the name of
+   the top module is set to "" in its constructor, the generated trace file
+   will have the verilog top module as its root, rather than another module
+   added by Verilator.
+
 .. option:: --trace-underscore
 
    Enable tracing of signals or modules that start with an

src/V3LinkLevel.cpp

@@ -289,6 +289,10 @@ void V3LinkLevel::wrapTopCell(AstNetlist* rootp) {
                         varp->trace(false);
                     }
 
+                    if (v3Global.opt.noTraceTop() && varp->isIO()) {
+                        varp->trace(false);
+                    }
+
                     AstPin* const pinp = new AstPin{
                         oldvarp->fileline(), 0, varp->name(),
                         new AstVarRef{varp->fileline(), varp,

src/V3Options.cpp

@@ -1496,6 +1496,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
     DECL_OPTION("-timing", OnOff, &m_timing);
     DECL_OPTION("-top-module", Set, &m_topModule);
     DECL_OPTION("-top", Set, &m_topModule);
+    DECL_OPTION("-no-trace-top", Set, &m_noTraceTop);
     DECL_OPTION("-trace", OnOff, &m_trace);
     DECL_OPTION("-trace-coverage", OnOff, &m_traceCoverage);
     DECL_OPTION("-trace-depth", Set, &m_traceDepth);

src/V3Options.h

@@ -280,6 +280,7 @@ private:
     bool m_traceCoverage = false;   // main switch: --trace-coverage
     bool m_traceParams = true;      // main switch: --trace-params
     bool m_traceStructs = false;    // main switch: --trace-structs
+    bool m_noTraceTop;              // main switch: --no-trace-top
     bool m_traceUnderscore = false; // main switch: --trace-underscore
     bool m_underlineZero = false;   // main switch: --underline-zero; undocumented old Verilator 2
     bool m_verilate = true;         // main switch: --verilate
@@ -578,6 +579,7 @@ public:
     bool protectKeyProvided() const { return !m_protectKey.empty(); }
     string protectKeyDefaulted() VL_MT_SAFE;  // Set default key if not set by user
     string topModule() const { return m_topModule; }
+    bool noTraceTop() const { return m_noTraceTop; }
     string unusedRegexp() const { return m_unusedRegexp; }
     string waiverOutput() const { return m_waiverOutput; }
     bool isWaiverOutput() const { return !m_waiverOutput.empty(); }

test_regress/t/t_no_trace_top.cpp

@@ -0,0 +1,44 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2008 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+
+#include <memory>
+
+#include VM_PREFIX_INCLUDE
+
+unsigned long long main_time = 0;
+double sc_time_stamp() { return (double)main_time; }
+
+int main(int argc, char** argv) {
+    Verilated::debug(0);
+    Verilated::traceEverOn(true);
+    Verilated::commandArgs(argc, argv);
+
+    std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"top"}};
+
+    std::unique_ptr<VerilatedVcdC> tfp{new VerilatedVcdC};
+    top->trace(tfp.get(), 99);
+    tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simno_trace_top.vcd");
+
+    top->clk = 0;
+
+    while (main_time < 1900) {  // Creates 2 files
+        top->clk = !top->clk;
+        top->eval();
+        tfp->dump((unsigned int)(main_time));
+        ++main_time;
+    }
+    tfp->close();
+    top->final();
+    tfp.reset();
+    top.reset();
+    printf("*-* All Finished *-*\n");
+    return 0;
+}

test_regress/t/t_no_trace_top.pl

@@ -0,0 +1,29 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2013 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt_all => 1);
+
+top_filename("t_trace_cat.v");
+
+compile(
+    make_top_shell => 0,
+    make_main => 0,
+    v_flags2 => ["--trace --no-trace-top --exe $Self->{t_dir}/t_no_trace_top.cpp"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+vcd_identical("$Self->{obj_dir}/simno_trace_top.vcd",
+              $Self->{golden_filename});
+
+ok(1);
+1;