From e94023367fdaca9b46929bca6a2031a870ac5b54 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 19 Jan 2023 17:44:27 -0500
Subject: [PATCH] Fix elaboration of member selected classes (#3890).

---
 Changes                                 |  1 +
 src/V3Width.cpp                         |  1 +
 test_regress/t/t_class_membersel_int.pl | 21 +++++++++++++++++++++
 test_regress/t/t_class_membersel_int.v  | 24 ++++++++++++++++++++++++
 4 files changed, 47 insertions(+)
 create mode 100755 test_regress/t/t_class_membersel_int.pl
 create mode 100644 test_regress/t/t_class_membersel_int.v

diff --git a/Changes b/Changes
index 82a4d6a70..b593efde9 100644
--- a/Changes
+++ b/Changes
@@ -30,6 +30,7 @@ Verilator 5.005 devel
 * Fix compatibility with musl libc / Alpine Linux (#3845). [Sören Tempel]
 * Fix empty case items crash (#3851). [rporter]
 * Fix foreach unnamedblk duplicate error (#3885). [Ilya Barkov]
+* Fix elaboration of member selected classes (#3890). [Ilya Barkov]
 
 
 Verilator 5.004 2022-12-14
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 65131acfd..32899dce3 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -2581,6 +2581,7 @@ private:
         } else if (AstClassRefDType* const adtypep = VN_CAST(fromDtp, ClassRefDType)) {
             if (AstNode* const foundp = memberSelClass(nodep, adtypep)) {
                 if (AstVar* const varp = VN_CAST(foundp, Var)) {
+                    if (!varp->didWidth()) userIterate(varp, nullptr);
                     nodep->dtypep(foundp->dtypep());
                     nodep->varp(varp);
                     return;
diff --git a/test_regress/t/t_class_membersel_int.pl b/test_regress/t/t_class_membersel_int.pl
new file mode 100755
index 000000000..859050d63
--- /dev/null
+++ b/test_regress/t/t_class_membersel_int.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_class_membersel_int.v b/test_regress/t/t_class_membersel_int.v
new file mode 100644
index 000000000..a0367f11d
--- /dev/null
+++ b/test_regress/t/t_class_membersel_int.v
@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+class Cls;
+   int t;
+endclass
+
+module Sub;
+   Cls c;
+   initial begin
+      int i;
+      c = new;
+      i = c.t;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+module t;
+   Sub foo;
+endmodule