diff --git a/Changes b/Changes
index d007f2117..5fd330aec 100644
--- a/Changes
+++ b/Changes
@@ -31,6 +31,7 @@ Verilator 5.023 devel
 * Fix DFG removing forceable signals (#4942). [Geza Lore]
 * Fix null characters in shortened identifiers (#4946). [Abdul Hameed]
 * Fix assignment of null into struct member (#4952).
+* Fix unpacked structure upper bit cleaning (#4978).
 
 
 Verilator 5.022 2024-02-24
diff --git a/src/V3Clean.cpp b/src/V3Clean.cpp
index fa118f4da..9acb79559 100644
--- a/src/V3Clean.cpp
+++ b/src/V3Clean.cpp
@@ -224,6 +224,11 @@ class CleanVisitor final : public VNVisitor {
         iterateChildren(nodep);
         setClean(nodep, true);
     }
+    void visit(AstConsPackMember* nodep) override {
+        iterateChildren(nodep);
+        ensureClean(nodep->rhsp());
+        setClean(nodep, true);
+    }
     void visit(AstSel* nodep) override {
         operandTriop(nodep);
         setClean(nodep, nodep->cleanOut());
diff --git a/test_regress/t/t_struct_unpacked_clean.pl b/test_regress/t/t_struct_unpacked_clean.pl
new file mode 100755
index 000000000..eacb5f80e
--- /dev/null
+++ b/test_regress/t/t_struct_unpacked_clean.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2=>["--x-assign unique --x-initial unique -Wno-WIDTH -O0"]
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_struct_unpacked_clean.v b/test_regress/t/t_struct_unpacked_clean.v
new file mode 100644
index 000000000..b1951a36d
--- /dev/null
+++ b/test_regress/t/t_struct_unpacked_clean.v
@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+
+typedef struct {
+   logic [4:0] w5;
+} Data_t;
+
+module t;
+
+    reg en;
+    reg [7:0] r_id;
+
+    Data_t ts;
+
+    initial begin
+       en = 1;
+       r_id = 42;
+       ts = '{w5: en ? r_id[4:0] : 5'b0};
+
+       $display("ts.w5 = %h", ts.w5);
+       if ($c32(ts.w5) != 5'h0a) $stop;
+       $write("*-* All Finished *-*\n");
+       $finish;
+    end
+endmodule