github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-01 04:07:34 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix $fscanf of decimals overflowing variables (#4174).

Browse Source
This commit is contained in:
Wilson Snyder 2023-05-07 08:25:10 -04:00
parent 0606a29f13
commit e6f5a0495f
4 changed files with 16 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Changes
View File

@ -28,6 +28,7 @@ Verilator 5.011 devel
* Fix linking AstRefDType if it has parameterized class ref (#4164) (#4170). [Ryszard Rozak, Antmicro Ltd]
* Fix crash caused by $display() optimization (#4165) (#4166). [Tudor Timi]
* Fix arrays of unpacked structs (#4173). [Risto Pejašinović]
* Fix $fscanf of decimals overflowing variables (#4174). [Ahmed El-Mahmoudy]
* Fix detection of wire/reg duplicates.
* Fix false IMPLICITSTATIC on package functions.

10
include/verilated.cpp
View File

@ -1373,16 +1373,18 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf
*p = t_tmp;
} else if (obits <= VL_BYTESIZE) {
CData* const p = va_arg(ap, CData*);
*p = owp[0];
*p = VL_CLEAN_II(obits, obits, owp[0]);
} else if (obits <= VL_SHORTSIZE) {
SData* const p = va_arg(ap, SData*);
*p = owp[0];
*p = VL_CLEAN_II(obits, obits, owp[0]);
} else if (obits <= VL_IDATASIZE) {
IData* const p = va_arg(ap, IData*);
*p = owp[0];
*p = VL_CLEAN_II(obits, obits, owp[0]);
} else if (obits <= VL_QUADSIZE) {
QData* const p = va_arg(ap, QData*);
*p = VL_SET_QW(owp);
*p = VL_CLEAN_QQ(obits, obits, VL_SET_QW(owp));
} else {
_vl_clean_inplace_w(obits, owp);
}
}
} // switch

2
src/V3EmitCFunc.h
View File

@ -792,7 +792,7 @@ public:
void visit(AstSysFuncAsTask* nodep) override {
if (!nodep->lhsp()->isWide()) puts("(void)");
iterateAndNextConstNull(nodep->lhsp());
if (!nodep->lhsp()->isWide()) puts(";");
if (!nodep->lhsp()->isWide()) puts(";\n");
}
void visit(AstStackTraceF* nodep) override { puts("VL_STACKTRACE_N()"); }
void visit(AstStackTraceT* nodep) override { puts("VL_STACKTRACE();\n"); }

8
test_regress/t/t_sys_file_basic.v
View File

@ -33,6 +33,9 @@ module t;
integer v_length, v_off;
wire signed [16:0] wire17 = 17'h1ffff;
logic signed [16:0] scan17;
`ifdef TEST_VERBOSE
`define verbose 1'b1
`else
@ -309,6 +312,11 @@ module t;
$fclose(file);
end
begin
$sscanf("-1", "%d", scan17);
if (scan17 !== wire17) $stop;
end
$write("*-* All Finished *-*\n");
$finish(0); // Test arguments to finish
end