Fix trace activity with --timing (#3576) (#3678) (#3696)

src/V3Trace.cpp

@@ -432,6 +432,12 @@ private:
         if (AstCCall* const callp = VN_CAST(insertp, CCall)) {
             callp->addNextHere(setterp);
         } else if (AstCFunc* const funcp = VN_CAST(insertp, CFunc)) {
+            // If there are awaits, insert the setter after each await
+            if (funcp->isCoroutine() && funcp->stmtsp()) {
+                funcp->stmtsp()->foreachAndNext<AstCAwait>([&](AstCAwait* awaitp) {
+                    if (awaitp->nextp()) awaitp->addNextHere(setterp->cloneTree(false));
+                });
+            }
             funcp->addStmtsp(setterp);
         } else {
             insertp->v3fatalSrc("Bad trace activity vertex");

test_regress/t/t_timing_clkgen1.v

@@ -4,8 +4,6 @@
 // any use, without warranty, 2020 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-`define STRINGIFY(x) `"x`"
-
 module clkgen(output bit clk);
    initial begin
       #(8.0:5:3) clk = 1;  // Middle is default
@@ -40,11 +38,4 @@ module t(/*AUTOARG*/);
          $finish;
       end
    end
-
-`ifdef TEST_TRACING
-   initial begin
-     $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
-     $dumpvars;
-   end
-`endif
 endmodule

test_regress/t/t_timing_clkgen_unsup.out

@@ -1,5 +1,5 @@
-%Warning-MINTYPMAXDLY: t/t_timing_clkgen1.v:11:13: Unsupported: minimum/typical/maximum delay expressions. Using the typical delay
-   11 |       #(8.0:5:3) clk = 1;   
+%Warning-MINTYPMAXDLY: t/t_timing_clkgen1.v:9:13: Unsupported: minimum/typical/maximum delay expressions. Using the typical delay
+    9 |       #(8.0:5:3) clk = 1;   
       |             ^
                        ... For warning description see https://verilator.org/warn/MINTYPMAXDLY?v=latest
                        ... Use "/* verilator lint_off MINTYPMAXDLY */" and lint_on around source to disable this message.

test_regress/t/t_timing_trace.out

@@ -1,67 +1,76 @@
 $version Generated by VerilatedVcd $end
-$date Wed Oct  5 13:59:40 2022 $end
+$date Thu Oct 20 09:56:59 2022 $end
 $timescale 1ps $end
 
  $scope module TOP $end
   $scope module t $end
-   $var wire  1 # clk $end
-   $var wire 32 $ cyc [31:0] $end
-   $scope module clkgen $end
-    $var wire  1 # clk $end
-   $upscope $end
+   $var wire 32 * CLK_HALF_PERIOD [31:0] $end
+   $var wire 32 ) CLK_PERIOD [31:0] $end
+   $var wire  1 $ a $end
+   $var wire  1 % b $end
+   $var wire  1 & c $end
+   $var wire  1 ( clk $end
+   $var wire  1 ' d $end
+   $var wire  1 # rst $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-0#
-b00000000000000000000000000000000 $
-#5
 1#
-b00000000000000000000000000000001 $
+0$
+0%
+0&
+0'
+0(
+b00000000000000000000000000001010 )
+b00000000000000000000000000000101 *
+#5
+1(
 #10
 0#
+1%
+0(
 #15
-1#
-b00000000000000000000000000000010 $
+1(
 #20
-0#
+0(
 #25
-1#
-b00000000000000000000000000000011 $
+1(
 #30
-0#
+0(
 #35
-1#
-b00000000000000000000000000000100 $
+1(
 #40
-0#
+0(
 #45
-1#
-b00000000000000000000000000000101 $
+1(
 #50
-0#
+0(
 #55
-1#
-b00000000000000000000000000000110 $
+1(
 #60
-0#
+0(
 #65
-1#
-b00000000000000000000000000000111 $
+1(
 #70
-0#
+0(
 #75
-1#
-b00000000000000000000000000001000 $
+1(
 #80
-0#
+0(
 #85
-1#
-b00000000000000000000000000001001 $
+1(
 #90
-0#
+0(
 #95
+1(
+#100
+0(
+#105
+1(
+#110
 1#
-b00000000000000000000000000001010 $
+0%
+0(

test_regress/t/t_timing_trace.pl

@@ -14,10 +14,8 @@ if (!$Self->have_coroutines) {
     skip("No coroutine support");
 }
 else {
-    top_filename("t/t_timing_clkgen1.v");
-
     compile(
-        verilator_flags2 => ["--exe --main --timing --trace -Wno-MINTYPMAXDLY -DTEST_TRACING"],
+        verilator_flags2 => ["--exe --main --timing --trace -Wno-MINTYPMAXDLY"],
         make_main => 0,
         );
 

test_regress/t/t_timing_trace.v

@@ -0,0 +1,43 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+`define STRINGIFY(x) `"x`"
+
+module t;
+    localparam CLK_PERIOD = 10;
+    localparam CLK_HALF_PERIOD = CLK_PERIOD / 2;
+
+    logic rst;
+    logic clk;
+    logic a;
+    logic b;
+    logic c;
+    logic d;
+
+    initial begin
+        $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+        $dumpvars;
+        forever clk = #CLK_HALF_PERIOD ~clk;
+    end
+
+    always begin
+        rst = 1;
+        clk = 0;
+        a = 0;
+        c = 0;
+        b = 0;
+        d = 0;
+
+        #CLK_PERIOD;
+        rst = 0;
+        b = 1;
+
+        #(10 * CLK_PERIOD);
+
+        $write("*-* All Finished *-*\n");
+        $finish;
+    end
+endmodule