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Fix constification of $realtobits, $bitstoreal (#4522).

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This commit is contained in:
Wilson Snyder 2023-09-28 22:45:00 -04:00
parent 2385ab8294
commit e49ae663a6
4 changed files with 25 additions and 8 deletions
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@ -15,6 +15,7 @@ Verilator 5.017 devel
* Add trace() API even when Verilated without --trace (#4462). [phelter]
* Add warning on interface instantiation without parens (#4094). [Gökçe Aydos]
* Fix constification of $realtobits, $bitstoreal (#4522). [Andrew Nolte]
* Support randc (#4349).
* Support resizing function call inout arguments (#4467).

20
src/V3Number.cpp
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@ -2388,19 +2388,23 @@ V3Number& V3Number::opRToIRoundS(const V3Number& lhs) {
V3Number& V3Number::opRealToBits(const V3Number& lhs) {
NUM_ASSERT_OP_ARGS1(lhs);
NUM_ASSERT_DOUBLE_ARGS1(lhs);
// Conveniently our internal format is identical so we can copy bits...
if (lhs.width() != 64 || width() != 64) v3fatalSrc("Real operation on wrong sized number");
m_data.setLogic();
opAssign(lhs);
return *this;
union {
double m_d;
uint64_t m_v;
} u;
u.m_d = lhs.toDouble();
return setQuad(u.m_v);
}
V3Number& V3Number::opBitsToRealD(const V3Number& lhs) {
NUM_ASSERT_OP_ARGS1(lhs);
// Conveniently our internal format is identical so we can copy bits...
if (lhs.width() != 64 || width() != 64) v3fatalSrc("Real operation on wrong sized number");
m_data.setDouble();
opAssign(lhs);
return *this;
union {
double m_d;
uint64_t m_v;
} u;
u.m_v = lhs.toUQuad();
return setDouble(u.m_d);
}
V3Number& V3Number::opNegateD(const V3Number& lhs) {
NUM_ASSERT_OP_ARGS1(lhs);

4
test_regress/t/t_math_real.v
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@ -97,6 +97,10 @@ module t (/*AUTOARG*/
for (r=1.0; r<2.0; r=r+0.1) i++;
if (i!=10) $stop;
// bug
ci64 = $realtobits(1.444);
if (ci64 != 64'h3ff71a9fbe76c8b4) $stop;
r = $bitstoreal(64'h3ff71a9fbe76c8b4);
if (r != 1.444) $stop;
r = $bitstoreal($realtobits(1.414));
if (r != 1.414) $stop;
// bug

8
test_regress/t/t_package.v
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@ -23,6 +23,12 @@ package p2;
function [3:0] plustwo(input [3:0] i);
plustwo = i+2;
endfunction
function automatic bit realCompare(real r);
logic [63:0] b = $realtobits(r);
return b > 0;
endfunction
endpackage
module t (/*AUTOARG*/
@ -55,10 +61,12 @@ endmodule
module t2;
import p::*;
import p2::plustwo;
import p2::realCompare;
import p2::package2_type_t;
package_type_t vp;
package2_type_t vp2;
initial begin
bit x = realCompare(1.0);
if (plusone(1) !== 2) $stop;
if (plustwo(1) !== 3) $stop;
if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value