From e47208d9b303c37e585a4a2a6719e6ade7c901cc Mon Sep 17 00:00:00 2001
From: Yilou Wang <wangyilou123@gmail.com>
Date: Wed, 6 Nov 2024 23:31:48 +0100
Subject: [PATCH] Support queue's assignment `push_back/push_front('{})`
 (#5585) (#5586)

Co-authored-by: Udaya Raj Subedi <075bei047.udaya@pcampus.edu.np>
---
 src/V3Width.cpp                      |  4 ++-
 test_regress/t/t_queue_assignment.py | 18 ++++++++++++
 test_regress/t/t_queue_assignment.v  | 41 ++++++++++++++++++++++++++++
 3 files changed, 62 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_queue_assignment.py
 create mode 100644 test_regress/t/t_queue_assignment.v

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 6d5621da4..87760c0bb 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3129,7 +3129,9 @@ class WidthVisitor final : public VNVisitor {
         // Any AstWith is checked later when know types, in methodWithArgument
         for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) {
             if (AstArg* const argp = VN_CAST(pinp, Arg)) {
-                if (argp->exprp()) userIterate(argp->exprp(), WidthVP{SELF, BOTH}.p());
+                if (argp->exprp())
+                    userIterate(argp->exprp(),
+                                WidthVP{nodep->fromp()->dtypep()->subDTypep(), BOTH}.p());
             }
         }
         // Find the fromp dtype - should be a class
diff --git a/test_regress/t/t_queue_assignment.py b/test_regress/t/t_queue_assignment.py
new file mode 100755
index 000000000..d4f986441
--- /dev/null
+++ b/test_regress/t/t_queue_assignment.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_queue_assignment.v b/test_regress/t/t_queue_assignment.v
new file mode 100644
index 000000000..80f52ca52
--- /dev/null
+++ b/test_regress/t/t_queue_assignment.v
@@ -0,0 +1,41 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by PlanV GmbH.
+// SPDX-License-Identifier: CC0-1.0
+
+module t_queue_assignment;
+    typedef int T_QI[$];
+    T_QI jagged_array[$];   // int jagged_array[$][$];
+    initial begin
+        jagged_array = '{ {1}, T_QI'{2,3,4}, {5,6} };
+        // jagged_array[0][0] = 1 -- jagged_array[0] is a queue of 1 int
+        // jagged_array[1][0] = 2 -- jagged_array[1] is a queue of 3 ints
+        // jagged_array[1][1] = 3
+        // jagged_array[1][2] = 4
+        // jagged_array[2][0] = 5 -- jagged_array[2] is a queue of 2 ints
+        // jagged_array[2][1] = 6
+        jagged_array.push_back('{7});
+        jagged_array.push_back('{8, 9, 10});
+        jagged_array.push_front('{0, 1});
+        print_and_check();
+
+        $write("*-* All Finished *-*\n");
+        $finish;
+    end
+
+    task automatic print_and_check();
+        integer i, j;
+        int expected_values[][] = '{ '{0, 1}, '{1}, '{2, 3, 4}, '{5, 6}, '{7}, '{8, 9, 10} };
+
+        for (i = 0; i < jagged_array.size(); i++) begin
+            for (j = 0; j < jagged_array[i].size(); j++) begin
+                // $display("jagged_array[%0d][%0d] = %0d", i, j, jagged_array[i][j]);
+                if (jagged_array[i][j] !== expected_values[i][j]) begin
+                    $stop;
+                end
+            end
+        end
+    endtask
+
+endmodule