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README.rst
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@ -28,7 +28,7 @@ Welcome to Verilator
- |Logo| - |Logo|
* - |verilator multithreaded performance| * - |verilator multithreaded performance|
- **Fast** - **Fast**
* Outperforms many commercial simulators * Outperforms many closed-source commercial simulators
* Single- and multi-threaded output models * Single- and multi-threaded output models
* - **Widely Used** * - **Widely Used**
* Wide industry and academic deployment * Wide industry and academic deployment
@ -55,20 +55,19 @@ performing lint checks, and optionally inserting assertion checks and
coverage-analysis points. It outputs single- or multi-threaded .cpp and .h coverage-analysis points. It outputs single- or multi-threaded .cpp and .h
files, the "Verilated" code. files, the "Verilated" code.
The user writes a little C++/SystemC wrapper file, which instantiates the These Verilated C++/SystemC files are then compiled by a C++ compiler
"Verilated" model of the user's top level module. These C++/SystemC files (gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper
are then compiled by a C++ compiler (gcc/clang/MSVC++). Executing the file to instantiate the Verilated model. Executing the resulting executable
resulting executable performs the design simulation. Verilator also performs the design simulation. Verilator also supports linking Verilated
supports linking Verilated generated libraries, optionally encrypted, into generated libraries, optionally encrypted, into other simulators.
other simulators.
Verilator may not be the best choice if you are expecting a full featured Verilator may not be the best choice if you are expecting a full featured
replacement for Incisive, ModelSim/Questa, VCS or another commercial replacement for a closed-source Verilog simulator, need SDF annotation,
Verilog simulator, or if you are looking for a behavioral Verilog simulator mixed-signal simulation, or are doing a quick class project (we recommend
e.g. for a quick class project (we recommend `Icarus Verilog`_ for this.) `Icarus Verilog`_ for classwork.) However, if you are looking for a path
However, if you are looking for a path to migrate SystemVerilog to C++ or to migrate SystemVerilog to C++/SystemC, or want high speed simulation of
SystemC, or your team is comfortable writing just a touch of C++ code, synthesizable designs containing limited verification constructs, Verilator
Verilator is the tool for you. is the tool for you.
Performance Performance
@ -85,9 +84,11 @@ multithreading (yielding 200-1000x total over interpreted simulators).
Verilator has typically similar or better performance versus the Verilator has typically similar or better performance versus the
closed-source Verilog simulators (Carbon Design Systems Carbonator, closed-source Verilog simulators (Carbon Design Systems Carbonator,
Modelsim, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and
CVer/CVC). But, Verilator is open-sourced, so you can spend on computes Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on
rather than licenses. Thus Verilator gives you the best cycles/dollar. computes rather than licenses. Thus Verilator gives you the best
cycles/dollar.
Installation & Documentation Installation & Documentation
============================ ============================