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This commit is contained in:
Wilson Snyder 2013-01-13 19:51:15 -05:00
parent 7a8184d206
commit e41e26717b
3 changed files with 4 additions and 5 deletions
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5
bin/verilator
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@ -202,9 +202,8 @@ Verilator - Convert Verilog code to C++/SystemC
verilator --help
verilator --version
verilator --cc [options] [top_level.v] [opt_c_files.cpp/c/cc/a/o/so]
verilator --sc [options] [top_level.v] [opt_c_files.cpp/c/cc/a/o/so]
verilator --sp [options] [top_level.v] [opt_c_files.cpp/c/cc/a/o/so]
verilator --cc [options] [top_level.v]... [opt_c_files.cpp/c/cc/a/o/so]
verilator --sc [options] [top_level.v]... [opt_c_files.cpp/c/cc/a/o/so]
verilator --lint-only [top_level.v]...
=head1 DESCRIPTION

2
src/V3WidthSel.cpp
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@ -218,7 +218,7 @@ private:
if (debug()>=9) newp->dumpTree(cout,"--SELBTn: ");
nodep->replaceWith(newp); pushDeletep(nodep); nodep=NULL;
}
else if (ddtypep->castNodeClassDType()) {
else if (ddtypep->castNodeClassDType()) { // It's packed, so a bit from the packed struct
// SELBIT(range, index) -> SEL(array, index, 1)
AstSel* newp = new AstSel (nodep->fileline(),
fromp,

2
test_regress/t/t_EXAMPLE.v
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@ -13,7 +13,7 @@
// please note it here, otherwise:**
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
// without warranty, 2013 by ____YOUR_NAME_HERE____.
module t (/*AUTOARG*/
// Inputs