diff --git a/test_regress/t/t_delay.v b/test_regress/t/t_delay.v
index 2c1d2d9c6..7434c1841 100644
--- a/test_regress/t/t_delay.v
+++ b/test_regress/t/t_delay.v
@@ -17,19 +17,29 @@ module t (/*AUTOARG*/
    wire [31:0] dly1;
    wire [31:0] dly2 = dly1 + 32'h1;
 
+   typedef struct packed { int dly; } dly_s_t;
+   dly_s_t dly_s;
+
    assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
 
    always @ (posedge clk) begin
       cyc <= cyc + 1;
-      if (cyc==1) begin
+      if (cyc == 1) begin
          dly0 <= #0 32'h11;
       end
-      else if (cyc==2) begin
+      else if (cyc == 2) begin
          dly0 <= #0.12 dly0 + 32'h12;
       end
-      else if (cyc==3) begin
+      else if (cyc == 3) begin
          if (dly0 !== 32'h23) $stop;
          if (dly2 !== 32'h25) $stop;
+      end
+      else if (cyc == 4) begin
+         dly_s.dly = 55;
+         dly0 <= #(dly_s.dly) 32'h55;
+         //dly0 <= # dly_s.dly 32'h55;  // Unsupported, issue-2410
+      end
+      else if (cyc == 99) begin
          $write("*-* All Finished *-*\n");
          #100 $finish;
       end
diff --git a/test_regress/t/t_delay_stmtdly_bad.out b/test_regress/t/t_delay_stmtdly_bad.out
index f52d97869..9a680e713 100644
--- a/test_regress/t/t_delay_stmtdly_bad.out
+++ b/test_regress/t/t_delay_stmtdly_bad.out
@@ -1,15 +1,26 @@
-%Warning-ASSIGNDLY: t/t_delay.v:20:13: Unsupported: Ignoring delay on this assignment/primitive.
-   20 |    assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
+%Warning-ASSIGNDLY: t/t_delay.v:23:13: Unsupported: Ignoring delay on this assignment/primitive.
+   23 |    assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
       |             ^~~~~~~~~~~~~~~~~~
                     ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
-%Warning-ASSIGNDLY: t/t_delay.v:25:19: Unsupported: Ignoring delay on this assignment/primitive.
-   25 |          dly0 <= #0 32'h11;
-      |                   ^
 %Warning-ASSIGNDLY: t/t_delay.v:28:19: Unsupported: Ignoring delay on this assignment/primitive.
-   28 |          dly0 <= #0.12 dly0 + 32'h12;
+   28 |          dly0 <= #0 32'h11;
+      |                   ^
+%Warning-ASSIGNDLY: t/t_delay.v:31:19: Unsupported: Ignoring delay on this assignment/primitive.
+   31 |          dly0 <= #0.12 dly0 + 32'h12;
       |                   ^~~~
-%Warning-STMTDLY: t/t_delay.v:34:11: Unsupported: Ignoring delay on this delayed statement.
+%Warning-ASSIGNDLY: t/t_delay.v:39:25: Unsupported: Ignoring delay on this assignment/primitive.
+   39 |          dly0 <= #(dly_s.dly) 32'h55;
+      |                         ^
+%Warning-STMTDLY: t/t_delay.v:44:11: Unsupported: Ignoring delay on this delayed statement.
                                    : ... In instance t
-   34 |          #100 $finish;
+   44 |          #100 $finish;
       |           ^~~
+%Warning-UNUSED: t/t_delay.v:21:12: Signal is not used: 'dly_s'
+                                  : ... In instance t
+   21 |    dly_s_t dly_s;
+      |            ^~~~~
+%Warning-BLKSEQ: t/t_delay.v:38:20: Blocking assignments (=) in sequential (flop or latch) block
+                                  : ... Suggest delayed assignments (<=)
+   38 |          dly_s.dly = 55;
+      |                    ^
 %Error: Exiting due to