Tests: Fill in some missing error coverage holes.

test_regress/t/t_interface_modport_bad.out

@@ -0,0 +1,2 @@
+%Error: t/t_interface_modport_bad.v:22: Modport not found under interface 'ifc': oop_modport
+%Error: Exiting due to

test_regress/t/t_interface_modport_bad.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_interface_modport_bad.v

@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2013 by Wilson Snyder.
+
+interface ifc;
+   integer ok;
+   modport out_modport (output ok);
+endinterface
+
+module t (/*AUTOARG*/);
+
+   ifc itop();
+
+   counter_ansi c1 (.isub(itop),
+                    .i_value(4'h4));
+
+endmodule
+
+module counter_ansi
+  (
+   ifc.oop_modport isub,  // Bad
+   input logic [3:0] i_value
+   );
+endmodule

test_regress/t/t_lint_import_name_bad.out

@@ -0,0 +1,2 @@
+%Error: t/t_lint_import_name_bad.v:10: Import object not found: defs::sigs
+%Error: Exiting due to

test_regress/t/t_lint_import_name_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_lint_import_name_bad.v

@@ -0,0 +1,13 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Wilson Snyder.
+
+package defs;
+   int sig;
+endpackage
+
+import defs::sigs;
+
+module t;
+endmodule

test_regress/t/t_var_notfound_bad.out

@@ -1,7 +1,9 @@
-%Error: t/t_var_notfound_bad.v:14: Can't find definition of variable: nf
-%Error: t/t_var_notfound_bad.v:15: Can't find definition of 'subsubz' in dotted scope/variable: sub.subsubz
+%Error: t/t_var_notfound_bad.v:17: Can't find definition of variable: nf
+%Error: t/t_var_notfound_bad.v:18: Can't find definition of 'subsubz' in dotted scope/variable: sub.subsubz
         ... Known scopes under 'sub': subsub
-%Error: t/t_var_notfound_bad.v:16: Can't find definition of task/function: nofunc
-%Error: t/t_var_notfound_bad.v:17: Can't find definition of task/function: notask
-%Error: t/t_var_notfound_bad.v:18: Found definition of 'a_var' as a VAR but expected a task/function
+%Error: t/t_var_notfound_bad.v:19: Can't find definition of task/function: nofunc
+%Error: t/t_var_notfound_bad.v:20: Can't find definition of 'nofuncs' in dotted task/function: sub.nofuncs
+        ... Known scopes under 'nofuncs': <no cells found>
+%Error: t/t_var_notfound_bad.v:21: Can't find definition of task/function: notask
+%Error: t/t_var_notfound_bad.v:22: Found definition of 'a_var' as a VAR but expected a task/function
 %Error: Exiting due to

test_regress/t/t_var_notfound_bad.v

@@ -10,10 +10,14 @@ module t (/*AUTOARG*/);
 
    sub sub ();
 
+   task nottask(); endtask
+   function int notfunc(); return 0; endfunction
+
    initial begin
       nf = 0;  // z not found
       sub.subsubz.inss = 0;  // subsub not found
       i = nofunc();  // nofunc not found
+      i = sub.nofuncs();  // nofuncs not found
       notask();  // notask not found
       a_var();  // Calling variable as task
       $finish;
@@ -22,6 +26,7 @@ endmodule
 
 module sub;
    subsub subsub ();
+   function int notfuncs(); return 0; endfunction
 endmodule
 
 module subsub;

test_regress/t/t_var_port2_bad.out

@@ -0,0 +1,3 @@
+%Error: t/t_var_port2_bad.v:6: Input/output/inout declaration not found for port: portwithoin
+%Error: t/t_var_port2_bad.v:7: Input/output/inout does not appear in port list: portwithin
+%Error: Exiting due to

test_regress/t/t_var_port2_bad.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(linter => 1);
+
+compile(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_var_port2_bad.v

@@ -0,0 +1,8 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (portwithoin);
+   input portwithin;
+endmodule

test_regress/t/t_var_suggest_bad.out

@@ -0,0 +1,3 @@
+%Error: t/t_var_suggest_bad.v:12: Can't find definition of variable: foobat
+%Error: t/t_var_suggest_bad.v:13: Can't find definition of task/function: boobat
+%Error: Exiting due to

test_regress/t/t_var_suggest_bad.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(linter => 1);
+
+lint(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_var_suggest_bad.v

@@ -0,0 +1,15 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t;
+   reg foobar;
+
+   task boobar; endtask
+
+   initial begin
+      if (foobat) $stop;
+      boobat;
+   end
+endmodule