Define VL_PRINTF by default, and remove old coverageRequest

git-svn-id: file://localhost/svn/verilator/trunk/verilator@786 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -3,6 +3,12 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.60**
+
+**** Add default define for VL_PRINTF.  [John Stroebel]
+
+**** Removed coverage request variable; see Coverage limitations in docs.
+
 * Verilator 3.602 09/11/2006
 
 **** Fix function references under top inlined module.  [David Hewson]

bin/verilator

@@ -248,9 +248,9 @@ Specifies basic block line coverage analysis code should be inserted.
 
 Coverage analysis adds statements at each code flow change point, which are
 the branches of IF and CASE statements, a superset of normal Verilog Line
-Coverage.  At each such branch a C++ macro is called, which SystemPerl uses
+Coverage.  At each such branch a unique counter is incremented.  At the end
-to increment an array.  At the end of a test, logs/coverage.pl is written
+of a test, the counters along with the filename and line number
-with the data from the array.
+corresponding to each counter are written into logs/coverage.pl.
 
 After running multiple tests, the vcoverage utility (from the SystemPerl
 package) is executed.  Vcoverage reads the logs/coverage.pl file(s), and
@@ -261,6 +261,10 @@ them, as it is assumed $stop branches contain an error check that should
 not occur.  A /*verilator coverage_block_off*/ comment will perform a
 similar function on any code in that block or below.
 
+Note Verilator may over-count combinatorial (non-clocked) blocks when those
+blocks receive signals which have had the UNOPTFLAT warning disabled; for
+most accurate results do not disable this warning when using coverage.
+
 For an example, after running 'make test' in the Verilator distribution,
 see the test_sp/logs/coverage_source directory.  Grep for lines starting
 with '%' to see what lines Verilator believes need more coverage.
@@ -936,9 +940,9 @@ each different output width.
 
 =item $display, $write, $fdisplay, $fwrite
 
-$display format arguments may use C fprintf sizes after the % escape.  Per
+Format arguments may use C fprintf sizes after the % escape.  Per the
-the Verilog standard, %x prints a number with the natural width, %0x prints
+Verilog standard, %x prints a number with the natural width, %0x prints a
-a number with minimum width, however %5x prints 5 digits per the C standard
+number with minimum width, however %5x prints 5 digits per the C standard
 (it's unspecified in Verilog).
 
 =item $fopen, $fclose, $fdisplay, $fwrite
@@ -1248,6 +1252,11 @@ will give a width warning and wrap around the power-of-2 size.  For
 non-power-of-2 sizes, it will return a unspecified constant of the
 appropriate width.
 
+=item $display, $write, $fdisplay, $fwrite
+
+$display and friends must have a constant format string as the first
+argument (as with C's printf), you cannot simply list variables standalone.
+
 =head1 ERRORS
 
 Warnings may be disabled in two ways.  First, when the warning is

include/verilated.h

@@ -115,6 +115,13 @@ public:
 
 #endif
 
+//=========================================================================
+// Functions overridable by user defines
+
+#ifndef VL_PRINTF
+# define VL_PRINTF printf	///< Print ala printf; may redefine if desired
+#endif
+
 //===========================================================================
 /// Verilator global static information class
 

src/V3EmitC.cpp

@@ -217,8 +217,7 @@ public:
 	puts(");\n");
     }
     virtual void visit(AstCoverInc* nodep, AstNUser*) {
-	puts("if (VL_LIKELY(vlSymsp->__Vm_coverageRequest))");
+	puts("++this->__Vcoverage[");
-	puts(" ++this->__Vcoverage[");
 	puts(cvtToStr(m_coverIds.remap(nodep->declp()))); puts("];\n");
     }
     virtual void visit(AstCReturn* nodep, AstNUser*) {
@@ -1246,12 +1245,8 @@ void EmitCImp::emitWrapEval(AstModule* modp) {
     puts("while (VL_LIKELY(__Vchange)) {\n");
     puts(    "VL_DEBUG_IF(cout<<\" Clock loop\"<<endl;);\n");
 #endif
-    // Not exactly correct for coverage.  w/combo logic interspersed, this is complicated.  Punt.
-    // Perhaps have temp & each _combo_ turn it on or off
-    if (v3Global.opt.coverage()) puts(    "vlSymsp->__Vm_coverageRequest = true;\n");
     puts(    "vlSymsp->__Vm_activity = true;\n");
     puts(    "_eval(vlSymsp);\n");
-    if (v3Global.opt.coverage()) puts(    "vlSymsp->__Vm_coverageRequest = false;\n");
 #ifndef NEW_ORDERING
     puts(    "__Vchange = _change_request(vlSymsp);\n");
     puts(    "if (++__VclockLoop > 100) vl_fatal(__FILE__,__LINE__,__FILE__,\"Verilated model didn't converge\");\n");

src/V3EmitCSyms.cpp

@@ -130,10 +130,6 @@ void EmitCSyms::emitInt() {
     puts("bool\t__Vm_activity;\t\t///< Used by trace routines to determine change occurred\n");
     ofp()->putAlign(V3OutFile::AL_AUTO, sizeof(bool));
     puts("bool\t__Vm_didInit;\n");
-    if (v3Global.opt.coverage()) {
-	ofp()->putAlign(V3OutFile::AL_AUTO, sizeof(bool));
-	puts("bool	 __Vm_coverageRequest;\n");
-    }
 
     ofp()->putAlign(V3OutFile::AL_AUTO, sizeof(uint64_t));
     puts("\n// SUBCELL STATE\n");
@@ -184,7 +180,6 @@ void EmitCSyms::emitImp() {
     puts("\t: __Vm_namep(namep)\n");	// No leak, as we get destroyed when the top is destroyed
     puts("\t, __Vm_activity(false)\n");
     puts("\t, __Vm_didInit(false)\n");
-    if (v3Global.opt.coverage()) puts("\t, __Vm_coverageRequest(false)\n");
     puts("\t// Setup submodule names\n");
     char comma=',';
     for (vector<ScopeModPair>::iterator it = m_scopes.begin(); it != m_scopes.end(); ++it) {