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https://github.com/verilator/verilator.git
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df2746de71
@ -372,6 +372,7 @@ detailed descriptions of these arguments.
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--make <build-tool> Generate scripts for specified build tool
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--make <build-tool> Generate scripts for specified build tool
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-MAKEFLAGS <flags> Arguments to pass to make during --build
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-MAKEFLAGS <flags> Arguments to pass to make during --build
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--main Generate C++ main() file
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--main Generate C++ main() file
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--main-top-name Specify top name passed to Verilated model in generated C++ main
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--max-num-width <value> Maximum number width (default: 64K)
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--max-num-width <value> Maximum number width (default: 64K)
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--Mdir <directory> Name of output object directory
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--Mdir <directory> Name of output object directory
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--MMD Create .d dependency files
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--MMD Create .d dependency files
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@ -25,6 +25,7 @@ David Horton
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David Metz
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David Metz
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David Stanford
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David Stanford
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David Turner
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David Turner
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Don Williamson
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Drew Ranck
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Drew Ranck
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Drew Taussig
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Drew Taussig
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Driss Hafdi
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Driss Hafdi
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@ -808,6 +808,13 @@ Summary:
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See also :vlopt:`--binary`.
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See also :vlopt:`--binary`.
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.. option:: --main-top-name <string>
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Specify the name passed to the Verilated model being constructed, in the
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generated C++ main() function.
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If the string ``"-"`` is used, no top level scope is added.
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.. option:: --max-num-width <value>
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.. option:: --max-num-width <value>
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Set the maximum number literal width (e.g., in 1024'd22 this
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Set the maximum number literal width (e.g., in 1024'd22 this
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@ -51,6 +51,14 @@ private:
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// Not defining main_time/vl_time_stamp, so
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// Not defining main_time/vl_time_stamp, so
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v3Global.opt.addCFlags("-DVL_TIME_CONTEXT"); // On MSVC++ anyways
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v3Global.opt.addCFlags("-DVL_TIME_CONTEXT"); // On MSVC++ anyways
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// Optional main top name argument, with empty string replacement
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string topArg;
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string topName = v3Global.opt.mainTopName();
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if (!topName.empty()) {
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if (topName == "-") topName = "";
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topArg = ", \"" + topName + "\"";
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}
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// Heavily commented output, as users are likely to look at or copy this code
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// Heavily commented output, as users are likely to look at or copy this code
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ofp()->putsHeader();
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ofp()->putsHeader();
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puts("// DESCRIPTION: main() calling loop, created with Verilator --main\n");
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puts("// DESCRIPTION: main() calling loop, created with Verilator --main\n");
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@ -71,7 +79,7 @@ private:
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puts("// Construct the Verilated model, from Vtop.h generated from Verilating\n");
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puts("// Construct the Verilated model, from Vtop.h generated from Verilating\n");
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puts("const std::unique_ptr<" + topClassName() + "> topp{new " + topClassName()
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puts("const std::unique_ptr<" + topClassName() + "> topp{new " + topClassName()
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+ "{contextp.get()}};\n");
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+ "{contextp.get()" + topArg + "}};\n");
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puts("\n");
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puts("\n");
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puts("// Simulate until $finish\n");
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puts("// Simulate until $finish\n");
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@ -1279,6 +1279,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
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DECL_OPTION("-l2-name", Set, &m_l2Name);
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DECL_OPTION("-l2-name", Set, &m_l2Name);
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DECL_OPTION("-no-l2name", CbCall, [this]() { m_l2Name = ""; }).undocumented(); // Historical
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DECL_OPTION("-no-l2name", CbCall, [this]() { m_l2Name = ""; }).undocumented(); // Historical
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DECL_OPTION("-l2name", CbCall, [this]() { m_l2Name = "v"; }).undocumented(); // Historical
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DECL_OPTION("-l2name", CbCall, [this]() { m_l2Name = "v"; }).undocumented(); // Historical
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DECL_OPTION("-main-top-name", Set, &m_mainTopName);
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DECL_OPTION("-MAKEFLAGS", CbVal, callStrSetter(&V3Options::addMakeFlags));
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DECL_OPTION("-MAKEFLAGS", CbVal, callStrSetter(&V3Options::addMakeFlags));
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DECL_OPTION("-MMD", OnOff, &m_makeDepend);
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DECL_OPTION("-MMD", OnOff, &m_makeDepend);
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@ -330,6 +330,7 @@ private:
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string m_flags; // main switch: -f {name}
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string m_flags; // main switch: -f {name}
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string m_l2Name; // main switch: --l2name; "" for top-module's name
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string m_l2Name; // main switch: --l2name; "" for top-module's name
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string m_libCreate; // main switch: --lib-create {lib_name}
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string m_libCreate; // main switch: --lib-create {lib_name}
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string m_mainTopName; // main switch: --main-top-name
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string m_makeDir; // main switch: -Mdir
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string m_makeDir; // main switch: -Mdir
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string m_modPrefix; // main switch: --mod-prefix
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string m_modPrefix; // main switch: --mod-prefix
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string m_pipeFilter; // main switch: --pipe-filter
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string m_pipeFilter; // main switch: --pipe-filter
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@ -567,6 +568,7 @@ public:
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}
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}
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return libName;
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return libName;
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}
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}
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string mainTopName() const { return m_mainTopName; }
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string makeDir() const VL_MT_SAFE { return m_makeDir; }
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string makeDir() const VL_MT_SAFE { return m_makeDir; }
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string modPrefix() const VL_MT_SAFE { return m_modPrefix; }
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string modPrefix() const VL_MT_SAFE { return m_modPrefix; }
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string pipeFilter() const { return m_pipeFilter; }
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string pipeFilter() const { return m_pipeFilter; }
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28
test_regress/t/t_flag_main_top_name.pl
Normal file
28
test_regress/t/t_flag_main_top_name.pl
Normal file
@ -0,0 +1,28 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2023 by Don Williamson and Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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top_filename("t/t_flag_main_top_name.v");
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compile(
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verilator_flags => ["-Mdir $Self->{obj_dir}", "--exe", "--build", "--main"],
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verilator_flags2 => ["--top-module top", "--main-top-name ALTOP"],
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verilator_make_cmake => 0,
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verilator_make_gmake => 0,
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make_main => 0,
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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22
test_regress/t/t_flag_main_top_name.v
Normal file
22
test_regress/t/t_flag_main_top_name.v
Normal file
@ -0,0 +1,22 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2023 by Don Williamson and Wilson Snyder. This program is free software; you
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// can redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module top;
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string scope;
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initial begin
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scope = $sformatf("%m");
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$write("[%0t] In %s\n", $time, scope);
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`ifdef MAIN_TOP_NAME_EMPTY
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if (scope != "top") $stop;
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`else
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if (scope != "ALTOP.top") $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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28
test_regress/t/t_flag_main_top_name_empty.pl
Normal file
28
test_regress/t/t_flag_main_top_name_empty.pl
Normal file
@ -0,0 +1,28 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2023 by Don Williamson and Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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top_filename("t/t_flag_main_top_name.v");
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compile(
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verilator_flags => ["-Mdir $Self->{obj_dir}", "--exe", "--build", "--main"],
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verilator_flags2 => ["--top-module top", "--main-top-name -", "-DMAIN_TOP_NAME_EMPTY"],
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verilator_make_cmake => 0,
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verilator_make_gmake => 0,
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make_main => 0,
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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