diff --git a/src/verilog.l b/src/verilog.l
index 1faf7a4bc..3740b4736 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -163,6 +163,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "$atan2"              { FL; return yD_ATAN2; }
   "$atanh"              { FL; return yD_ATANH; }
   "$bitstoreal"         { FL; return yD_BITSTOREAL; }
+  "$bitstoshortreal"    { FL; return yD_BITSTOSHORTREAL; }
   "$ceil"               { FL; return yD_CEIL; }
   "$cos"                { FL; return yD_COS; }
   "$cosh"               { FL; return yD_COSH; }
@@ -206,6 +207,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "$setuphold"          { FL; return yaTIMINGSPEC; }
   "$sformat"            { FL; return yD_SFORMAT; }
   "$sformatf"           { FL; return yD_SFORMATF; }
+  "$shortrealtobits"    { FL; return yD_SHORTREALTOBITS; }
   "$sin"                { FL; return yD_SIN; }
   "$sinh"               { FL; return yD_SINH; }
   "$skew"               { FL; return yaTIMINGSPEC; }
diff --git a/src/verilog.y b/src/verilog.y
index 94db470d0..d3074fae5 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -224,6 +224,10 @@ static void ERRSVKWD(FileLine* fileline, const string& tokname) {
                         : ""));
 }
 
+static void UNSUPREAL(FileLine* fileline) {
+    fileline->v3warn(SHORTREAL, "Unsupported: shortreal being promoted to real (suggest use real instead)");
+}
+							  
 //======================================================================
 
 class AstSenTree;
@@ -493,6 +497,7 @@ class AstSenTree;
 %token<fl>		yD_ATANH	"$atanh"
 %token<fl>		yD_BITS		"$bits"
 %token<fl>		yD_BITSTOREAL	"$bitstoreal"
+%token<fl>		yD_BITSTOSHORTREAL "$bitstoshortreal"
 %token<fl>		yD_C		"$c"
 %token<fl>		yD_CEIL		"$ceil"
 %token<fl>		yD_CLOG2	"$clog2"
@@ -543,6 +548,7 @@ class AstSenTree;
 %token<fl>		yD_RTOI		"$rtoi"
 %token<fl>		yD_SFORMAT	"$sformat"
 %token<fl>		yD_SFORMATF	"$sformatf"
+%token<fl>		yD_SHORTREALTOBITS "$shortrealtobits"
 %token<fl>		yD_SIGNED	"$signed"
 %token<fl>		yD_SIN		"$sin"
 %token<fl>		yD_SINH		"$sinh"
@@ -1425,8 +1431,7 @@ integer_vector_type<bdtypep>:	// ==IEEE: integer_atom_type
 non_integer_type<bdtypep>:	// ==IEEE: non_integer_type
 		yREAL					{ $$ = new AstBasicDType($1,AstBasicDTypeKwd::DOUBLE); }
 	|	yREALTIME				{ $$ = new AstBasicDType($1,AstBasicDTypeKwd::DOUBLE); }
-	|	ySHORTREAL				{ $1->v3warn(SHORTREAL, "Unsupported: shortreal being promoted to real (suggest use real instead)");
-							  $$ = new AstBasicDType($1,AstBasicDTypeKwd::DOUBLE); }
+	|	ySHORTREAL				{ $$ = new AstBasicDType($1,AstBasicDTypeKwd::DOUBLE); UNSUPREAL($1); }
 	;
 
 signingE<signstate>:		// IEEE: signing - plus empty
@@ -2913,6 +2918,7 @@ system_f_call_or_t<nodep>:	// IEEE: part of system_tf_call (can be task or func)
 	|	yD_BITS '(' exprOrDataType ')'		{ $$ = new AstAttrOf($1,AstAttrType::DIM_BITS,$3); }
 	|	yD_BITS '(' exprOrDataType ',' expr ')'	{ $$ = new AstAttrOf($1,AstAttrType::DIM_BITS,$3,$5); }
 	|	yD_BITSTOREAL '(' expr ')'		{ $$ = new AstBitsToRealD($1,$3); }
+	|	yD_BITSTOSHORTREAL '(' expr ')'		{ $$ = new AstBitsToRealD($1,$3); UNSUPREAL($1); }
 	|	yD_CEIL '(' expr ')'			{ $$ = new AstCeilD($1,$3); }
 	|	yD_CLOG2 '(' expr ')'			{ $$ = new AstCLog2($1,$3); }
 	|	yD_COS '(' expr ')'			{ $$ = new AstCosD($1,$3); }
@@ -2960,6 +2966,7 @@ system_f_call_or_t<nodep>:	// IEEE: part of system_tf_call (can be task or func)
 	|	yD_RIGHT '(' exprOrDataType ',' expr ')'	{ $$ = new AstAttrOf($1,AstAttrType::DIM_RIGHT,$3,$5); }
 	|	yD_RTOI '(' expr ')'			{ $$ = new AstRToIS($1,$3); }
 	|	yD_SFORMATF '(' str commaEListE ')'	{ $$ = new AstSFormatF($1,*$3,false,$4); }
+	|	yD_SHORTREALTOBITS '(' expr ')'		{ $$ = new AstRealToBits($1,$3); UNSUPREAL($1); }
 	|	yD_SIGNED '(' expr ')'			{ $$ = new AstSigned($1,$3); }
 	|	yD_SIN '(' expr ')'			{ $$ = new AstSinD($1,$3); }
 	|	yD_SINH '(' expr ')'			{ $$ = new AstSinhD($1,$3); }
diff --git a/test_regress/t/t_math_shortreal.v b/test_regress/t/t_math_shortreal.v
index 146e0463d..b9d1500e8 100644
--- a/test_regress/t/t_math_shortreal.v
+++ b/test_regress/t/t_math_shortreal.v
@@ -78,7 +78,7 @@ module t (/*AUTOARG*/
       for (r=1.0; r<2.0; r=r+0.1) i++;
       if (i!=10) $stop;
       // bug
-      r = $bitstoreal($realtobits(1.414));
+      r = $bitstoshortreal($shortrealtobits(1.414));
       if (r != 1.414) $stop;
    end