From deda8773559743759ee66f78e49d799bef617c07 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 16 Dec 2009 11:21:25 -0500 Subject: [PATCH] Allow --lint-only to ignore UDP tables --- src/V3LinkResolve.cpp | 22 +++++- test_regress/t/t_udp.v | 147 +++++++++++++++++++++++++++++++++++ test_regress/t/t_udp_lint.pl | 21 +++++ 3 files changed, 189 insertions(+), 1 deletion(-) create mode 100644 test_regress/t/t_udp.v create mode 100755 test_regress/t/t_udp_lint.pl diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp index 50bfd6a25..0db8593fd 100644 --- a/src/V3LinkResolve.cpp +++ b/src/V3LinkResolve.cpp @@ -336,7 +336,27 @@ private: virtual void visit(AstUdpTable* nodep, AstNUser*) { UINFO(5,"UDPTABLE "<v3error("Unsupported: Verilog 1995 UDP Tables"); + if (!v3Global.opt.lintOnly()) { + nodep->v3error("Unsupported: Verilog 1995 UDP Tables"); + } else { + // Massive hack, just tie off all outputs so our analysis can proceed + AstVar* varoutp = NULL; + for (AstNode* stmtp = m_modp->stmtsp(); stmtp; stmtp=stmtp->nextp()) { + if (AstVar* varp = stmtp->castVar()) { + if (varp->isInput()) { + } else if (varp->isOutput()) { + if (varoutp) { varp->v3error("Multiple outputs not allowed in udp modules"); } + varoutp = varp; + // Tie off + m_modp->addStmtp(new AstAssignW(varp->fileline(), + new AstVarRef(varp->fileline(), varp, true), + new AstConst(varp->fileline(), AstConst::LogicFalse()))); + } else { + varp->v3error("Only inputs and outputs are allowed in udp modules"); + } + } + } + } nodep->unlinkFrBack(); pushDeletep(nodep); nodep=NULL; } diff --git a/test_regress/t/t_udp.v b/test_regress/t/t_udp.v new file mode 100644 index 000000000..1bdaa6ec5 --- /dev/null +++ b/test_regress/t/t_udp.v @@ -0,0 +1,147 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + // Async clears must not race with clocks if we want repeatable results + reg set_l = in[20]; + reg clr_l = in[21]; + always @ (negedge clk) begin + set_l <= in[20]; + clr_l <= in[21]; + end + + //====== Mux + wire [1:0] qm; + // z a b sel + udp_mux2 m0 (qm[0], in[0], in[2], in[4]); + udp_mux2 m1 (qm[1], in[1], in[3], in[4]); + +`define verilatorxx +`ifdef verilatorxx + reg [1:0] ql; + reg [1:0] qd; + + initial $display("****FIXME: No sequential tables\n"); +// always @* begin +// if (!clk) ql = in[13:12]; +// end + always @(posedge clk or negedge set_l or negedge clr_l) begin + if (!set_l) qd <= ~2'b0; + else if (!clr_l) qd <= 2'b0; + else qd <= in[17:16]; + end +`else + //====== Latch +// wire [1:0] ql; +// // q clk d +// udp_latch l0 (ql[0], !in[8], in[12]); +// udp_latch l1 (ql[1], !in[8], in[13]); + + //====== DFF + wire [1:0] qd; + //always @* $display("UL q=%b c=%b d=%b", ql[1:0], in[8], in[13:12]); + // q clk d set_l clr_l + udp_dff d0 (qd[0], in[8], in[16], set_l, clr_l); + udp_dff d2 (qd[1], in[8], in[17], set_l, clr_l); +`endif + + // Aggregate outputs into a single result vector + wire [63:0] result = {52'h0, 2'b0,qd, 4'b0, 2'b0,qm}; +// wire [63:0] result = {52'h0, 2'b0,qd, 2'b0,ql, 2'b0,qm}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + // Note not all simulators agree about the latch result. Maybe have a race? +`define EXPECTED_SUM 64'hb73acf228acaeaa3 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +primitive udp_mux2 (z, a, b, sel); + output z; + input a, b, sel; + table + //a b s o + ? 1 1 : 1 ; + ? 0 1 : 0 ; + 1 ? 0 : 1 ; + 0 ? 0 : 0 ; + 1 1 x : 1 ; + 0 0 x : 0 ; + endtable +endprimitive + +primitive udp_latch (q, clk, d); + output q; reg q; + input clk, d; + table + //clk d q q' + 0 1 : ? : 1; + 0 0 : ? : 0; + 1 ? : ? : -; + endtable +endprimitive + +primitive udp_dff (q, clk, d, set_l, clr_l); + output q; + input clk, d, set_l, clr_l; + reg q; + table + //ck d s c : q : q' + r 0 1 ? : ? : 0 ; + r 1 ? 1 : ? : 1 ; + * 1 ? 1 : 1 : 1 ; + * 0 1 ? : 0 : 0 ; + f ? ? ? : ? : - ; + b * ? ? : ? : - ; + ? ? 0 ? : ? : 1 ; + b ? * 1 : 1 : 1 ; + x 1 * 1 : 1 : 1 ; + ? ? 1 0 : ? : 0 ; + b ? 1 * : 0 : 0 ; + x 0 1 * : 0 : 0 ; + endtable +endprimitive diff --git a/test_regress/t/t_udp_lint.pl b/test_regress/t/t_udp_lint.pl new file mode 100755 index 000000000..7600eec23 --- /dev/null +++ b/test_regress/t/t_udp_lint.pl @@ -0,0 +1,21 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +top_filename("t/t_udp.v"); + +compile ( + # Unsupported: UDP Tables + make_top_shell => 0, + make_main => 0, + v_flags2 => ["--lint-only"], + verilator_make_gcc => 0, + ); + +ok(1); +1;