diff --git a/Changes b/Changes index 863b817ad..474d46e74 100644 --- a/Changes +++ b/Changes @@ -5,6 +5,8 @@ The contributors that suggested a given feature are shown in []. Thanks! * Verilator 4.005 devel +** Add --pp-comments, msg2700. [Robert Henry] + ** Add --dump-defines. *** For --trace-fst, save enum decoding information, bug1358. [Sergi Granell] diff --git a/bin/verilator b/bin/verilator index 10569b379..eb1b1cf03 100755 --- a/bin/verilator +++ b/bin/verilator @@ -339,6 +339,7 @@ detailed descriptions in L for more information. --pins-sc-biguint Specify types for top level ports --pins-uint8 Specify types for top level ports --pipe-filter Filter all input through a script + --pp-comments Show preprocessor comments with -E --prefix Name of top level class --prof-cfuncs Name functions for profiling --prof-threads Enable generating gantt chart data for threads @@ -1093,6 +1094,10 @@ t/t_pipe_filter test for an example. To debug the output of the filter, try using the -E option to see preprocessed output. +=item --pp-comments + +With -E, show comments in preprocessor output. + =item --prefix I Specifies the name of the top level class and makefile. Defaults to V diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 433453cc1..474243b2c 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -682,6 +682,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char else if ( onoff (sw, "-pins-sc-uint", flag/*ref*/) ){ m_pinsScUint = flag; if (!m_pinsScBigUint) m_pinsBv = 65; } else if ( onoff (sw, "-pins-sc-biguint", flag/*ref*/) ){ m_pinsScBigUint = flag; m_pinsBv = 513; } else if ( onoff (sw, "-pins-uint8", flag/*ref*/) ){ m_pinsUint8 = flag; } + else if ( onoff (sw, "-pp-comments", flag/*ref*/) ) { m_ppComments = flag; } else if ( !strcmp (sw, "-private") ) { m_public = false; } else if ( onoff (sw, "-prof-cfuncs", flag/*ref*/) ) { m_profCFuncs = flag; } else if ( onoff (sw, "-profile-cfuncs", flag/*ref*/) ) { m_profCFuncs = flag; } // Undocumented, for backward compat @@ -1267,6 +1268,7 @@ V3Options::V3Options() { m_pinsScUint = false; m_pinsScBigUint = false; m_pinsUint8 = false; + m_ppComments = false; m_profCFuncs = false; m_profThreads = false; m_preprocOnly = false; diff --git a/src/V3Options.h b/src/V3Options.h index 7e1c4958a..914d64c55 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -127,6 +127,7 @@ class V3Options { bool m_pinsScUint; // main switch: --pins-sc-uint bool m_pinsScBigUint;// main switch: --pins-sc-biguint bool m_pinsUint8; // main switch: --pins-uint8 + bool m_ppComments; // main switch: --pp-comments bool m_profCFuncs; // main switch: --prof-cfuncs bool m_profThreads; // main switch: --prof-threads bool m_public; // main switch: --public @@ -299,6 +300,7 @@ class V3Options { bool pinsScUint() const { return m_pinsScUint; } bool pinsScBigUint() const { return m_pinsScBigUint; } bool pinsUint8() const { return m_pinsUint8; } + bool ppComments() const { return m_ppComments; } bool profCFuncs() const { return m_profCFuncs; } bool profThreads() const { return m_profThreads; } bool allPublic() const { return m_public; } diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp index 784a09ab0..ab21f96e0 100644 --- a/src/V3PreProc.cpp +++ b/src/V3PreProc.cpp @@ -390,6 +390,12 @@ bool V3PreProcImp::commentTokenMatch(string& cmdr, const char* strg) { void V3PreProcImp::comment(const string& text) { // Comment detected. Only keep relevant data. + bool printed = false; + if (v3Global.opt.preprocOnly() && v3Global.opt.ppComments()) { + insertUnreadback(text); + printed = true; + } + const char* cp = text.c_str(); if (cp[0]=='/' && (cp[1]=='/' || cp[1]=='*')) { cp+=2; @@ -431,16 +437,16 @@ void V3PreProcImp::comment(const string& text) { if (v3Global.opt.assertOn()) { // one_hot, one_cold, (full_case, parallel_case) if (commentTokenMatch(cmd/*ref*/, "full_case")) { - insertUnreadback("/*verilator full_case*/"); + if (!printed) insertUnreadback("/*verilator full_case*/"); } if (commentTokenMatch(cmd/*ref*/, "parallel_case")) { - insertUnreadback("/*verilator parallel_case*/"); + if (!printed) insertUnreadback("/*verilator parallel_case*/"); } //if (commentTokenMatch(cmd/*ref*/, "one_hot")) { - // insertUnreadback ("/*verilator one_hot*/ "+cmd+";"); + // insertUnreadback ("/*verilator one_hot*/ "+cmd+";"); //} //if (commentTokenMatch(cmd/*ref*/, "one_cold")) { - // insertUnreadback ("/*verilator one_cold*/ "+cmd+";"); + // insertUnreadback ("/*verilator one_cold*/ "+cmd+";"); //} // else ignore the comment we don't recognize } // else no assertions @@ -450,9 +456,9 @@ void V3PreProcImp::comment(const string& text) { // "/*verilator public_flat_rw @(foo) */" -> "/*verilator public_flat_rw*/ @(foo)" cmd = cmd.substr(pos+strlen("public_flat_rw")); while (isspace(cmd[0])) cmd = cmd.substr(1); - insertUnreadback("/*verilator public_flat_rw*/ "+cmd+" /**/"); + if (!printed) insertUnreadback("/*verilator public_flat_rw*/ "+cmd+" /**/"); } else { - insertUnreadback("/*verilator "+cmd+"*/"); + if (!printed) insertUnreadback("/*verilator "+cmd+"*/"); } } } diff --git a/test_regress/t/t_preproc_comments.out b/test_regress/t/t_preproc_comments.out new file mode 100644 index 000000000..1618f90ff --- /dev/null +++ b/test_regress/t/t_preproc_comments.out @@ -0,0 +1,959 @@ +`line 1 "t/t_preproc.v" 1 +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2000-2011 by Wilson Snyder. + +`line 5 "t/t_preproc.v" 0 +//=========================================================================== +// Includes + +`line 7 "t/t_preproc.v" 0 +`line 1 "t/t_preproc_inc2.vh" 1 +// DESCRIPTION: Verilog::Preproc: Example source code +`line 2 "t/t_preproc_inc2.vh" 0 +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2000-2007 by Wilson Snyder. +At file "t/t_preproc_inc2.vh" line 4 + + +`line 6 "t/t_preproc_inc2.vh" 0 +`line 1 "t/t_preproc_inc3.vh" 1 +`line 2 "inc3_a_filename_from_line_directive" 0 +// DESCRIPTION: Verilog::Preproc: Example source code +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2000-2007 by Wilson Snyder. + +`line 6 "inc3_a_filename_from_line_directive" 0 + + + + // FOO + At file "inc3_a_filename_from_line_directive" line 10 + +`line 12 "inc3_a_filename_from_line_directive" 0 + + // guard + +`line 15 "inc3_a_filename_from_line_directive" 0 + + + + +`line 19 "inc3_a_filename_from_line_directive" 2 +`line 6 "t/t_preproc_inc2.vh" 0 + + +`line 8 "t/t_preproc_inc2.vh" 2 +`line 7 "t/t_preproc.v" 0 + + +`line 9 "t/t_preproc.v" 0 +//=========================================================================== +// Comments + +`line 12 "t/t_preproc.v" 0 +/* verilator pass_thru comment */ + +`line 14 "t/t_preproc.v" 0 +// verilator pass_thru_comment2 + +`line 16 "t/t_preproc.v" 0 +//=========================================================================== +// Defines + +`line 19 "t/t_preproc.v" 0 + + +// DEF_A0 set by command line + wire [3:0] q = { + 1'b1 , + 1'b0 , + 1'b1 , + 1'b1 + }; + +`line 29 "t/t_preproc.v" 0 +text. + +`line 31 "t/t_preproc.v" 0 + + +foo /*this */ bar /* this too */ +foobar2 // but not + +`line 36 "t/t_preproc.v" 0 + + + + +`line 40 "t/t_preproc.v" 0 + + + + + +`line 45 "t/t_preproc.v" 0 +/*******COMMENT*****/ +first part +`line 46 "t/t_preproc.v" 0 + second part +`line 46 "t/t_preproc.v" 0 + third part +{ +`line 47 "t/t_preproc.v" 0 + a, +`line 47 "t/t_preproc.v" 0 + b, +`line 47 "t/t_preproc.v" 0 + c} +Line_Preproc_Check 48 + +`line 50 "t/t_preproc.v" 0 +//=========================================================================== + +`line 52 "t/t_preproc.v" 0 + + +`line 54 "t/t_preproc.v" 0 + + +deep deep + +`line 58 "t/t_preproc.v" 0 + + +"Inside: `nosubst" +"`nosubst" + +`line 63 "t/t_preproc.v" 0 + +x y LLZZ x y +p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s + + + +`line 69 "t/t_preproc.v" 0 +firstline comma","line LLZZ firstline comma","line + +`line 71 "t/t_preproc.v" 0 + +x y LLZZ "x" y // Simulators disagree here; some substitute "a" others do not + +`line 74 "t/t_preproc.v" 0 + +(a,b)(a,b) + +`line 77 "t/t_preproc.v" 0 + +$display("left side: \"right side\"") + +`line 80 "t/t_preproc.v" 0 + +bar_suffix more + +`line 83 "t/t_preproc.v" 0 + + + +`line 85 "t/t_preproc.v" 0 + $c("Zap(\"",bug1,"\");");; + +`line 86 "t/t_preproc.v" 0 + $c("Zap(\"","bug2","\");");; + +`line 88 "t/t_preproc.v" 0 +/* Define inside comment: `DEEPER and `WITHTICK */ +// More commentary: `zap(bug1); `zap("bug2"); + +`line 91 "t/t_preproc.v" 0 +//====================================================================== +// display passthru + +`line 94 "t/t_preproc.v" 0 + + + + + + + initial begin + //$display(`msg( \`, \`)); // Illegal + $display("pre thrupre thrumid thrupost post: \"right side\""); + $display("left side: \"right side\""); + $display("left side: \"right side\""); + $display("left_side: \"right_side\""); + $display("na: \"right_side\""); + $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\""); + $display("na: \"nana\""); + $display("left_side right_side // Doesn't expand: \"left_side right_side // Doesn't expand\""); // Results vary between simulators + $display(": \"\""); // Empty + $display("left side: \"right side\""); + $display("left side: \"right side\""); + $display("standalone"); + +`line 115 "t/t_preproc.v" 0 + // Unspecified when the stringification has multiple lines + + + $display("twoline: \"first second\""); + //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +`line 125 "t/t_preproc.v" 0 +//====================================================================== +// rt.cpan.org bug34429 + +`line 128 "t/t_preproc.v" 0 + + + + + +`line 133 "t/t_preproc.v" 0 +module add1 ( input wire d1, output wire o1); + +`line 134 "t/t_preproc.v" 0 +wire tmp_d1 = d1; +`line 134 "t/t_preproc.v" 0 +wire tmp_o1 = tmp_d1 + 1; +`line 134 "t/t_preproc.v" 0 +assign o1 = tmp_o1 ; // expansion is OK +endmodule +module add2 ( input wire d2, output wire o2); + +`line 137 "t/t_preproc.v" 0 +wire tmp_d2 = d2; +`line 137 "t/t_preproc.v" 0 +wire tmp_o2 = tmp_d2 + 1; +`line 137 "t/t_preproc.v" 0 +assign o2 = tmp_o2 ; // expansion is bad +endmodule + +`line 140 "t/t_preproc.v" 0 + + + + + + +`line 146 "t/t_preproc.v" 0 +// parameterized macro with arguments that are macros + + + + +`line 151 "t/t_preproc.v" 0 + +`line 151 "t/t_preproc.v" 0 + generate for (i=0; i<(3); i=i+1) begin +`line 151 "t/t_preproc.v" 0 + psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; +`line 151 "t/t_preproc.v" 0 + psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; +`line 151 "t/t_preproc.v" 0 + end endgenerate // ignorecmt + +`line 153 "t/t_preproc.v" 0 +//====================================================================== +// Quotes are legal in protected blocks. Grr. +module prot(); +`protected + I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) + #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] +`line 159 "t/t_preproc.v" 0 +`endprotected +endmodule +//" + +`line 163 "t/t_preproc.v" 0 +//====================================================================== +// macro call with define that has comma + + + + + + + + +`line 173 "t/t_preproc.v" 0 +begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end +begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end +begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more + +`line 177 "t/t_preproc.v" 0 +//====================================================================== +// include of parameterized file + + +`line 180 "t/t_preproc.v" 0 +`line 1 "t/t_preproc_inc4.vh" 1 +// DESCRIPTION: Verilog::Preproc: Example source code +`line 2 "t/t_preproc_inc4.vh" 0 +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2000-2011 by Wilson Snyder. + +`line 5 "t/t_preproc_inc4.vh" 0 + + +`line 7 "t/t_preproc_inc4.vh" 2 +`line 180 "t/t_preproc.v" 0 + +`line 181 "t/t_preproc.v" 0 + + + +`line 184 "t/t_preproc.v" 0 + + +`line 186 "t/t_preproc.v" 0 + + + + +`line 190 "t/t_preproc.v" 0 +//====================================================================== +// macro call with , in {} + +`line 193 "t/t_preproc.v" 0 + +$blah("ab,cd","e,f"); +$blah(this.logfile,vec); +$blah(this.logfile,vec[1,2,3]); +$blah(this.logfile,{blah.name(), " is not foo"}); + +`line 199 "t/t_preproc.v" 0 +//====================================================================== +// pragma/default net type + +`line 202 "t/t_preproc.v" 0 +`pragma foo = 1 +`default_nettype none +`default_nettype uwire + +`line 206 "t/t_preproc.v" 0 +//====================================================================== +// Ifdef + +`line 209 "t/t_preproc.v" 0 + + + + +`line 213 "t/t_preproc.v" 0 +Line_Preproc_Check 213 + +`line 215 "t/t_preproc.v" 0 +//====================================================================== +// bug84 + +`line 218 "t/t_preproc.v" 0 + // Hello, comments MIGHT not be legal /*more,,)cmts*/ // But newlines ARE legal... who speced THAT? + + +(p,q) + + + +`line 225 "t/t_preproc.v" 0 +(//Here x,y //Too) +Line_Preproc_Check 226 + +`line 228 "t/t_preproc.v" 0 +//====================================================================== +// defines split arguments + +`line 231 "t/t_preproc.v" 0 + + + + +beginend // 2001 spec doesn't require two tokens, so "beginend" ok +beginend // 2001 spec doesn't require two tokens, so "beginend" ok +"beginend" // No space "beginend" + +`line 239 "t/t_preproc.v" 0 +//====================================================================== +// bug106 + + + `\esc`def + +`line 245 "t/t_preproc.v" 0 +Not a \`define + +`line 247 "t/t_preproc.v" 0 +//====================================================================== +// misparsed comma in submacro + + + + +x,y)--bee submacro has comma paren + +`line 255 "t/t_preproc.v" 0 +//====================================================================== +// bug191 + +$display("10 %d %d", $bits(foo), 10); + +`line 260 "t/t_preproc.v" 0 +//====================================================================== +// 1800-2009 + + + +`line 265 "t/t_preproc.v" 0 + + + +`line 268 "t/t_preproc.v" 0 +//====================================================================== +// bug202 + + + + + + + + + + + + +`line 282 "t/t_preproc.v" 0 + +`line 282 "t/t_preproc.v" 0 + +`line 282 "t/t_preproc.v" 0 + +`line 282 "t/t_preproc.v" 0 + +`line 282 "t/t_preproc.v" 0 + +`line 282 "t/t_preproc.v" 0 + +`line 282 "t/t_preproc.v" 0 + +`line 282 "t/t_preproc.v" 0 + +`line 282 "t/t_preproc.v" 0 + +`line 282 "t/t_preproc.v" 0 + assign a3 = ~b3 ; +`line 282 "t/t_preproc.v" 0 + + +`line 284 "t/t_preproc.v" 0 + +/* multi \ + line1*/ \ +`line 286 "t/t_preproc.v" 0 + +/*multi \ + line2*/ + + + + + +`line 293 "t/t_preproc.v" 0 + +`line 293 "t/t_preproc.v" 0 + +`line 293 "t/t_preproc.v" 0 +/* multi + line 3*/ +`line 293 "t/t_preproc.v" 0 + def i + + +`line 295 "t/t_preproc.v" 0 +//====================================================================== + +`line 297 "t/t_preproc.v" 0 + + + + + +`line 301 "t/t_preproc.v" 0 + + + + + + +`line 307 "t/t_preproc.v" 0 +1 // verilator NOT IN DEFINE (nodef) +2 /* verilator PART OF DEFINE */ (hasdef) +3 +`line 309 "t/t_preproc.v" 0 +/* verilator NOT PART + OF DEFINE */ (nodef) +`line 310 "t/t_preproc.v" 0 +4 +`line 310 "t/t_preproc.v" 0 +/* verilator PART + OF DEFINE */ (nodef) +`line 311 "t/t_preproc.v" 0 +5 also in +`line 311 "t/t_preproc.v" 0 + also3 // CMT NOT (nodef) + + +HAS a NEW +`line 314 "t/t_preproc.v" 0 +LINE + +`line 316 "t/t_preproc.v" 0 +//====================================================================== + +`line 318 "t/t_preproc.v" 0 + + + + + + + + + + + + + +`line 331 "t/t_preproc.v" 0 + + + +`line 334 "t/t_preproc.v" 0 +EXP: clxx_scen +clxx_scen +EXP: clxx_scen +"clxx_scen" + +EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); + +`line 340 "t/t_preproc.v" 0 + do +`line 340 "t/t_preproc.v" 0 + /* synopsys translate_off */ +`line 340 "t/t_preproc.v" 0 + +`line 340 "t/t_preproc.v" 0 + +`line 340 "t/t_preproc.v" 0 + +`line 340 "t/t_preproc.v" 0 + if (start("t/t_preproc.v", 340)) begin +`line 340 "t/t_preproc.v" 0 + +`line 340 "t/t_preproc.v" 0 + message({"Blah-", "clx_scen", " end"}); +`line 340 "t/t_preproc.v" 0 + end +`line 340 "t/t_preproc.v" 0 + /* synopsys translate_on */ +`line 340 "t/t_preproc.v" 0 + while(0); + +`line 342 "t/t_preproc.v" 0 +//====================================================================== + +`line 344 "t/t_preproc.v" 0 + + + + + +`line 348 "t/t_preproc.v" 0 + +`line 348 "t/t_preproc.v" 0 + + +`line 349 "t/t_preproc.v" 0 + +//`ifndef def_fooed_2 `error "No def_fooed_2" `endif +EXP: This is fooed +This is fooed +EXP: This is fooed_2 +This is fooed_2 + +`line 356 "t/t_preproc.v" 0 +//====================================================================== + +np +np +//====================================================================== +// It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution? + + + + + +`line 367 "t/t_preproc.v" 0 + + + +`line 370 "t/t_preproc.v" 0 +//====================================================================== +// Metaprogramming + + + + + + +`line 378 "t/t_preproc.v" 0 + + + + +`line 382 "t/t_preproc.v" 0 +hello3hello3hello3 +hello4hello4hello4hello4 +//====================================================================== +// Include from stringification + + + +`line 388 "t/t_preproc.v" 0 +`line 1 "t/t_preproc_inc4.vh" 1 +// DESCRIPTION: Verilog::Preproc: Example source code +`line 2 "t/t_preproc_inc4.vh" 0 +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2000-2011 by Wilson Snyder. + +`line 5 "t/t_preproc_inc4.vh" 0 + + +`line 7 "t/t_preproc_inc4.vh" 2 +`line 388 "t/t_preproc.v" 0 + +`line 389 "t/t_preproc.v" 0 + +//====================================================================== +// Defines doing defines +// Note the newline on the end - required to form the end of a define + + + + + +`line 397 "t/t_preproc.v" 0 + + + + +Line_Preproc_Check 401 +//====================================================================== +// Quoted multiline - track line numbers, and insure \\n gets propagated + + + +Line_Preproc_Check 407 +"FOO \ + BAR " "arg_line1 \ + arg_line2" "FOO \ + BAR " +`line 410 "t/t_preproc.v" 0 +Line_Preproc_Check 410 +//====================================================================== +// bug283 + +`line 414 "t/t_preproc.v" 0 + + + +// EXP: abc + +abc + + + + +`line 424 "t/t_preproc.v" 0 + + + +EXP: sonet_frame +sonet_frame + +`line 430 "t/t_preproc.v" 0 + + +EXP: sonet_frame +sonet_frame +// This result varies between simulators + + +EXP: sonet_frame +sonet_frame + +`line 440 "t/t_preproc.v" 0 +// The existance of non-existance of a base define can make a difference + + +EXP: module zzz ; endmodule +module zzz ; endmodule +module zzz ; endmodule + +`line 447 "t/t_preproc.v" 0 + +EXP: module a_b ; endmodule +module a_b ; endmodule +module a_b ; endmodule + +`line 452 "t/t_preproc.v" 0 +//====================================================================== +// bug311 +integer/*NEED_SPACE*/ foo; +//====================================================================== +// bug441 +module t; + //----- + // case provided + // note this does NOT escape as suggested in the mail + + + + initial begin : \`LEX_CAT(a[0],_assignment) +`line 464 "t/t_preproc.v" 0 + $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end + //----- + // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from + // substituting and the \ staying in the expansion + // Note space after name is important so when substitute it has ending whitespace + + + initial begin : \a[0]_assignment_a[1] +`line 471 "t/t_preproc.v" 0 + $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end + + //----- + + + // RULE: Ignoring backslash does NOT allow an additional expansion level + // (Because ESC gets expanded then the \ has it's normal escape meaning) + initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end + + //----- + + + + // Similar to above; \ does not allow expansion after substitution + initial begin : \`CAT(ff,bb) +`line 485 "t/t_preproc.v" 0 + $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end + + //----- + + + // MUST: Unknown macro with backslash escape stays as escaped symbol name + initial begin : \`zzz +`line 491 "t/t_preproc.v" 0 + $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end + + //----- + + + + // SHOULD(simulator-dependant): Known macro with backslash escape expands + initial begin : \`FOO +`line 498 "t/t_preproc.v" 0 + $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end + // SHOULD(simulator-dependant): Prefix breaks the above + initial begin : \xx`FOO +`line 500 "t/t_preproc.v" 0 + $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end + + //----- + // MUST: Unknown macro not under call with backslash escape doesn't expand + + initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end + //----- + // MUST: Unknown macro not under call doesn't expand + + initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end + + //----- + // bug441 derivative + // SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above) + + initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz"); + + //----- + // RULE: Because there are quotes after substituting STR, the `A does NOT expand + + + initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz"); + + //---- + // bug845 + + initial $write("Slashed=`%s'\n", "1//2.3"); + //---- + // bug915 + + + initial +`line 531 "t/t_preproc.v" 0 + $display("%s%s","a1","b2c3\n"); +endmodule + +`line 534 "t/t_preproc.v" 0 +//====================================================================== +//bug1225 + +`line 537 "t/t_preproc.v" 0 + + +$display("RAM0"); +$display("CPU"); + +`line 542 "t/t_preproc.v" 0 + + + + + +`line 547 "t/t_preproc.v" 0 + +XXE_FAMILY = XXE_ + + + $display("XXE_ is defined"); + + +`line 554 "t/t_preproc.v" 0 + +XYE_FAMILY = XYE_ + + + $display("XYE_ is defined"); + + +`line 561 "t/t_preproc.v" 0 + +XXS_FAMILY = XXS_some + + + $display("XXS_some is defined"); + + +`line 568 "t/t_preproc.v" 0 + +XYS_FAMILY = XYS_foo + + + $display("XYS_foo is defined"); + + +`line 575 "t/t_preproc.v" 0 +//==== + +`line 577 "t/t_preproc.v" 0 + + + + + + + + +`line 585 "t/t_preproc.v" 0 + + + + + + + +`line 592 "t/t_preproc.v" 0 + + + + + + + +`line 599 "t/t_preproc.v" 0 + + + + + + + +`line 606 "t/t_preproc.v" 0 + + +`line 608 "t/t_preproc.v" 0 + // NEVER + +`line 610 "t/t_preproc.v" 0 +//bug1227 + +(.mySig (myInterface.pa5), + +`line 614 "t/t_preproc.v" 0 +//====================================================================== +// Stringify bug + +`line 617 "t/t_preproc.v" 0 + +`dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); + +`line 620 "t/t_preproc.v" 0 + + + + + + + + +`line 628 "t/t_preproc.v" 0 +module pcc2_cfg; + generate + +`line 630 "t/t_preproc.v" 0 + covergroup a @(posedge b); +`line 630 "t/t_preproc.v" 0 + c: coverpoint d iff ((c) === 1'b1); endgroup +`line 630 "t/t_preproc.v" 0 + a u_a; +`line 630 "t/t_preproc.v" 0 + initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); + endgenerate +endmodule + +`line 634 "t/t_preproc.v" 0 +//====================================================================== +// IEEE mandated predefines + // undefineall should have no effect on these +predef 0 0 +predef 1 1 +predef 2 2 +predef 3 3 +predef 10 10 +predef 11 11 +predef 20 20 +predef 21 21 +predef 22 22 +predef 23 23 +predef -2 -2 +predef -1 -1 +predef 0 0 +predef 1 1 +predef 2 2 +//====================================================================== +// After `undefineall above, for testing --dump-defines + + +`line 656 "t/t_preproc.v" 2 diff --git a/test_regress/t/t_preproc_comments.pl b/test_regress/t/t_preproc_comments.pl new file mode 100755 index 000000000..fb687c03c --- /dev/null +++ b/test_regress/t/t_preproc_comments.pl @@ -0,0 +1,25 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(vlt => 1); + +top_filename("t/t_preproc.v"); + +$Self->{golden_out} ||= "t/$Self->{name}.out"; +my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp"; + +compile( + verilator_flags2 => ['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --pp-comments'], + verilator_make_gcc => 0, + stdout_filename => $stdout_filename, + ); + +ok(files_identical($stdout_filename, $Self->{golden_out})); + +1;