github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-04-25 01:56:54 +00:00
Code Issues Packages Projects Releases Wiki Activity

Parse UDP Tables, and report single unsupported error

Browse Source
This commit is contained in:
Wilson Snyder 2009-11-20 19:53:40 -05:00
parent e479c8a553
commit d7a2362a76
4 changed files with 56 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
src/V3AstNodes.h
View File

@ -1961,6 +1961,25 @@ struct AstScopeName : public AstNode {
void scopeAttrp(AstNode* nodep) { addOp1p(nodep); }
};
struct AstUdpTable : public AstNode {
AstUdpTable(FileLine* fl, AstNode* bodysp)
: AstNode(fl) {
addNOp1p(bodysp);
}
ASTNODE_NODE_FUNCS(UdpTable, UDPTABLE)
AstUdpTableLine* bodysp() const { return op1p()->castUdpTableLine(); } // op1 = List of UdpTableLines
};
struct AstUdpTableLine : public AstNode {
string m_text;
public:
AstUdpTableLine(FileLine* fl, const string& text)
: AstNode(fl), m_text(text) {}
ASTNODE_NODE_FUNCS(UdpTableLine, UDPTABLELINE)
virtual string name() const { return m_text; }
string text() const { return m_text; }
};
//======================================================================
// non-ary ops

6
src/V3LinkResolve.cpp
View File

@ -320,6 +320,12 @@ private:
}
}
virtual void visit(AstUdpTable* nodep, AstNUser*) {
UINFO(5,"UDPTABLE "<<nodep<<endl);
nodep->v3error("Unsupported: Verilog 1995 UDP Tables");
nodep->unlinkFrBack(); pushDeletep(nodep); nodep=NULL;
}
virtual void visit(AstScCtor* nodep, AstNUser*) {
// Constructor info means the module must remain public
m_modp->modPublic(true);

15
src/verilog.l
View File

@ -132,7 +132,7 @@ void yyerrorf(const char* format, ...) {
%o 25000
%s V95 V01 V05 S05
%s STRING ATTRMODE
%s STRING ATTRMODE TABLE
%s PSL
%s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
%s IGNORE
@ -212,6 +212,7 @@ escid \\[^ \t\f\r\n]+
"endmodule" { FL; return yENDMODULE; }
"endprimitive" { FL; return yENDPRIMITIVE; }
"endspecify" { FL; return yENDSPECIFY; }
"endtable" { yyerrorf("Syntax error: ENDTABLE outside of TABLE"); }
"endtask" { FL; return yENDTASK; }
"for" { FL; return yFOR; }
"forever" { FL; return yFOREVER; }
@ -243,6 +244,7 @@ escid \\[^ \t\f\r\n]+
"specparam" { FL; return ySPECPARAM; }
"supply0" { FL; return ySUPPLY0; }
"supply1" { FL; return ySUPPLY1; }
"table" { yy_push_state(TABLE); FL; return yTABLE; }
"task" { FL; return yTASK; }
"time" { FL; return yTIME; }
"tri" { FL; return yTRI; }
@ -267,7 +269,6 @@ escid \\[^ \t\f\r\n]+
/* Generic unsupported warnings */
"cmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"deassign" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"endtable" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"event" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"force" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"fork" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
@ -292,7 +293,6 @@ escid \\[^ \t\f\r\n]+
"small" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"strong0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"strong1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"table" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"tran" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"tranif0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"tranif1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
@ -791,6 +791,15 @@ escid \\[^ \t\f\r\n]+
"(*"/{ws}*[^)] { yymore(); yy_push_state(ATTRMODE); } // Doesn't match (*)
}
/************************************************************************/
/* Tables */
<TABLE>\\{crnl} { yymore(); NEXTLINE(); }
<TABLE>{crnl} { NEXTLINE(); yymore(); }
<TABLE>";" { yylval.strp = PARSEP->newString(yytext,yyleng); return yaTABLELINE; }
<TABLE>"endtable" { yy_pop_state(); FL; return yENDTABLE; }
<TABLE>. { yymore(); }
<TABLE><<EOF>> { yyerrorf("EOF in TABLE"); yyleng = 0; yy_pop_state(); }
/************************************************************************/
/* Preprocessor */
/* Common for all SYSC header states */

21
src/verilog.y
View File

@ -191,6 +191,8 @@ class AstSenTree;
%token<fl> yaTIMINGSPEC "TIMING SPEC ELEMENT"
%token<strp> yaTABLELINE "TABLE LINE"
%token<strp> yaSCHDR "`systemc_header BLOCK"
%token<strp> yaSCINT "`systemc_ctor BLOCK"
%token<strp> yaSCIMP "`systemc_dtor BLOCK"
@ -264,6 +266,7 @@ class AstSenTree;
%token<fl> yENDPROGRAM "endprogram"
%token<fl> yENDPROPERTY "endproperty"
%token<fl> yENDSPECIFY "endspecify"
%token<fl> yENDTABLE "endtable"
%token<fl> yENDTASK "endtask"
%token<fl> yFINAL "final"
%token<fl> yFOR "for"
@ -310,6 +313,7 @@ class AstSenTree;
%token<fl> ySTATIC "static"
%token<fl> ySUPPLY0 "supply0"
%token<fl> ySUPPLY1 "supply1"
%token<fl> yTABLE "table"
%token<fl> yTASK "task"
%token<fl> yTIME "time"
%token<fl> yTIMEPRECISION "timeprecision"
@ -1224,7 +1228,7 @@ module_or_generate_item<nodep>: // ==IEEE: module_or_generate_item
// // IEEE: gate_instantiation + udp_instantiation + module_instantiation
// // not here, see etcInst in module_common_item
// // We joined udp & module definitions, so this goes here
//UNSUP combinational_body { $$ = $1; }
| table { $$ = $1; }
| module_common_item { $$ = $1; }
;
@ -2528,7 +2532,20 @@ strengthSpecE: // IEEE: drive_strength + pullup_strength + pulldown_strength +
//************************************************
// Tables
// Not supported
table<nodep>: // IEEE: combinational_body + sequential_body
yTABLE tableEntryList yENDTABLE { $$ = new AstUdpTable($1,$2); }
;
tableEntryList<nodep>: // IEEE: { combinational_entry | sequential_entry }
tableEntry { $$ = $1; }
| tableEntryList tableEntry { $$ = $1->addNext($2); }
;
tableEntry<nodep>: // IEEE: combinational_entry + sequential_entry
yaTABLELINE { $$ = new AstUdpTableLine(CRELINE(),*$1); }
| error { $$ = NULL; }
;
//************************************************
// Specify