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Tests: Add a case to cover the line using m_frozenNodes. (#2915)
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@ -57,7 +57,7 @@ module t(/*AUTOARG*/
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'hfab547b426149442
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`define EXPECTED_SUM 64'he78be35df15ae0ab
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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@ -80,7 +80,7 @@ module Test(/*AUTOARG*/
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output logic o;
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logic [3:0] tmp;
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logic [4:0] tmp;
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assign o = ^tmp;
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always_ff @(posedge clk) begin
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@ -100,6 +100,7 @@ module Test(/*AUTOARG*/
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tmp[1] <= ((32'd2 ** i) & 32'h10) == 32'b0; // replacePowShift
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tmp[2] <= ((d0 & d1) | (d0 & d2))^ ((d3 & d4) | (d5 & d4)); // replaceAndOr()
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tmp[3] <= d0 <-> d1; // replaceLogEq()
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tmp[4] <= i[0] & (i[1] & (i[2] & (i[3] | d[4]))); // ConstBitOpTreeVisitor::m_frozenNodes
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end
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endmodule
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