mirror of
https://github.com/verilator/verilator.git
synced 2025-01-05 22:27:35 +00:00
More cleanup of verilog.l
git-svn-id: file://localhost/svn/verilator/trunk/verilator@896 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder
parent
b4d9eb6ec4
commit
d6cb175f96
193
src/verilog.l
193
src/verilog.l
@ -105,9 +105,38 @@ escid \\[^ \t\f\r\n]+
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<INITIAL>.|\n {BEGIN STATE_VERILOG_RECENT; yyless(0); }
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/* Verilog 1995 */
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<V95,V01,V05,S05,PSL>{
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{ws} ; /* ignore white-space */
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\n {NEXTLINE();} /* Count line numbers */
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/* Extensions to Verilog set, some specified by PSL */
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"$c"[0-9]* {yylval.fileline = CRELINE(); return yD_C;} /*Verilator only*/
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/* System Tasks */
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"$display" {yylval.fileline = CRELINE(); return yD_DISPLAY;}
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"$fclose" {yylval.fileline = CRELINE(); return yD_FCLOSE;}
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"$fdisplay" {yylval.fileline = CRELINE(); return yD_FDISPLAY;}
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"$finish" {yylval.fileline = CRELINE(); return yD_FINISH;}
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"$fopen" {yylval.fileline = CRELINE(); return yD_FOPEN;}
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"$fullskew" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$fwrite" {yylval.fileline = CRELINE(); return yD_FWRITE;}
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"$hold" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$nochange" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$period" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$readmemb" {yylval.fileline = CRELINE(); return yD_READMEMB;}
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"$readmemh" {yylval.fileline = CRELINE(); return yD_READMEMH;}
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"$realtime" {yylval.fileline = CRELINE(); return yD_TIME;}
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"$recovery" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$recrem" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$removal" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$setup" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$setuphold" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$skew" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$stop" {yylval.fileline = CRELINE(); return yD_STOP;}
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"$time" {yylval.fileline = CRELINE(); return yD_TIME;}
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"$timeskew" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$width" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$write" {yylval.fileline = CRELINE(); return yD_WRITE;}
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/* Keywords */
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"always" {yylval.fileline = CRELINE(); return yALWAYS;}
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"and" {yylval.fileline = CRELINE(); return yAND;}
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"assign" {yylval.fileline = CRELINE(); return yASSIGN;}
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@ -154,61 +183,7 @@ escid \\[^ \t\f\r\n]+
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"wire" {yylval.fileline = CRELINE(); return yWIRE;}
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"xnor" {yylval.fileline = CRELINE(); return yXNOR;}
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"xor" {yylval.fileline = CRELINE(); return yXOR;}
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}
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<V01,V05,S05,PSL>{
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"endgenerate" {yylval.fileline = CRELINE(); return yENDGENERATE;}
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"generate" {yylval.fileline = CRELINE(); return yGENERATE;}
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"genvar" {yylval.fileline = CRELINE(); return yGENVAR;}
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"localparam" {yylval.fileline = CRELINE(); return yLOCALPARAM;}
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"signed" {yylval.fileline = CRELINE(); return ySIGNED;}
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}
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<V05,S05,PSL>{
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"uwire" {yylval.fileline = CRELINE(); return yWIRE;}
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}
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<S05,PSL>{
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"always_comb" {yylval.fileline = CRELINE(); return yALWAYS;}
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"always_ff" {yylval.fileline = CRELINE(); return yALWAYS;}
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"always_latch" {yylval.fileline = CRELINE(); return yALWAYS;}
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"final" {yylval.fileline = CRELINE(); return yFINAL;}
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}
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<V95,V01,V05,S05,PSL>{
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/* Extensions to Verilog set, some specified by PSL */
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"$bits" {yylval.fileline = CRELINE(); return yD_BITS;} /*Verilator only*/
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"$c"[0-9]* {yylval.fileline = CRELINE(); return yD_C;} /*Verilator only*/
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"$countones" {yylval.fileline = CRELINE(); return yD_COUNTONES;} /*Verilator only*/
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"$isunknown" {yylval.fileline = CRELINE(); return yD_ISUNKNOWN;} /*Verilator only*/
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"$onehot" {yylval.fileline = CRELINE(); return yD_ONEHOT;} /*Verilator only*/
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"$onehot0" {yylval.fileline = CRELINE(); return yD_ONEHOT0;} /*Verilator only*/
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/* Standard ones */
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"$display" {yylval.fileline = CRELINE(); return yD_DISPLAY;}
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"$fclose" {yylval.fileline = CRELINE(); return yD_FCLOSE;}
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"$fdisplay" {yylval.fileline = CRELINE(); return yD_FDISPLAY;}
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"$finish" {yylval.fileline = CRELINE(); return yD_FINISH;}
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"$fopen" {yylval.fileline = CRELINE(); return yD_FOPEN;}
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"$fullskew" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$fwrite" {yylval.fileline = CRELINE(); return yD_FWRITE;}
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"$hold" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$nochange" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$period" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$readmemb" {yylval.fileline = CRELINE(); return yD_READMEMB;}
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"$readmemh" {yylval.fileline = CRELINE(); return yD_READMEMH;}
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"$realtime" {yylval.fileline = CRELINE(); return yD_TIME;}
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"$recovery" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$recrem" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$removal" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$setup" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$setuphold" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$skew" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$stop" {yylval.fileline = CRELINE(); return yD_STOP;}
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"$time" {yylval.fileline = CRELINE(); return yD_TIME;}
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"$timeskew" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$width" {yylval.fileline = CRELINE(); return yTIMINGSPEC;}
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"$write" {yylval.fileline = CRELINE(); return yD_WRITE;}
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/* Special errors */
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/* Special errors */
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"$displayb" {yyerrorf("Unsupported: Use $display with %%b format instead: %s",yytext);}
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"$displayh" {yyerrorf("Unsupported: Use $display with %%x format instead: %s",yytext);}
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"$displayo" {yyerrorf("Unsupported: Use $display with %%o format instead: %s",yytext);}
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@ -221,41 +196,7 @@ escid \\[^ \t\f\r\n]+
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"$writeb" {yyerrorf("Unsupported: Use $write with %%b format instead: %s",yytext);}
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"$writeh" {yyerrorf("Unsupported: Use $write with %%x format instead: %s",yytext);}
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"$writeo" {yyerrorf("Unsupported: Use $write with %%o format instead: %s",yytext);}
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}
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<V01,V05,S05,PSL>{
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"$signed" {yylval.fileline = CRELINE(); return yD_SIGNED;}
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"$unsigned" {yylval.fileline = CRELINE(); return yD_UNSIGNED;}
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}
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<V95,V01,V05,S05,PSL>{
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"$"[a-zA-Z_$]+ {yyerrorf("Unsupported or unknown PLI call: %s",yytext);}
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}
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/*Entry into PSL; mode change */
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<V95,V01,V05,S05>{
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"psl" { yy_push_state(PSL); yylval.fileline = CRELINE(); return yPSL; }
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}
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<PSL>{
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"psl" { ; } // 'psl' may occur in middle of statement, so easier just to suppress
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"assert" {yylval.fileline = CRELINE(); return yASSERT;}
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"assume" {yylval.fileline = CRELINE(); return yASSERT;} //==assert
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"before_!" {yyerrorf("Illegal syntax, use before!_ instead of %s",yytext);}
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"clock" {yylval.fileline = CRELINE(); return yCLOCK;}
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"countones" {yylval.fileline = CRELINE(); return yD_COUNTONES;}
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"cover" {yylval.fileline = CRELINE(); return yCOVER;}
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"isunknown" {yylval.fileline = CRELINE(); return yD_ISUNKNOWN;}
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"onehot" {yylval.fileline = CRELINE(); return yD_ONEHOT; }
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"onehot0" {yylval.fileline = CRELINE(); return yD_ONEHOT0; }
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"until_!" {yyerrorf("Illegal syntax, use until!_ instead of %s",yytext);}
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"report" {yylval.fileline = CRELINE(); return yREPORT; }
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"true" {yylval.fileline = CRELINE(); return yTRUE; }
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}
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/*Verilog Reserved*/
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<V95,V01,V05,S05,PSL>{
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/* Generic unsupported warnings */
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"bufif0" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
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"bufif1" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
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"cmos" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
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@ -315,9 +256,18 @@ escid \\[^ \t\f\r\n]+
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/* Verilog 2001 */
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<V01,V05,S05,PSL>{
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/* Special hints */
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/* System Tasks */
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"$signed" {yylval.fileline = CRELINE(); return yD_SIGNED;}
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"$unsigned" {yylval.fileline = CRELINE(); return yD_UNSIGNED;}
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/* Keywords */
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"endgenerate" {yylval.fileline = CRELINE(); return yENDGENERATE;}
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"generate" {yylval.fileline = CRELINE(); return yGENERATE;}
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"genvar" {yylval.fileline = CRELINE(); return yGENVAR;}
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"localparam" {yylval.fileline = CRELINE(); return yLOCALPARAM;}
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"signed" {yylval.fileline = CRELINE(); return ySIGNED;}
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/* Special errors */
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"include" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented; probably you want `include instead: %s",yytext);}
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/* Generic warnings */
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/* Generic unsupported warnings */
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"automatic" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
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"cell" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
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"config" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
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@ -336,8 +286,26 @@ escid \\[^ \t\f\r\n]+
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"use" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
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}
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/* System Verilog */
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/* Verilog 2005 */
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<V05,S05,PSL>{
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/* Keywords */
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"uwire" {yylval.fileline = CRELINE(); return yWIRE;}
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}
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/* System Verilog 2005 */
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<S05,PSL>{
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/* System Tasks */
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"$bits" {yylval.fileline = CRELINE(); return yD_BITS;}
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"$countones" {yylval.fileline = CRELINE(); return yD_COUNTONES;}
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"$isunknown" {yylval.fileline = CRELINE(); return yD_ISUNKNOWN;}
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"$onehot" {yylval.fileline = CRELINE(); return yD_ONEHOT;}
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"$onehot0" {yylval.fileline = CRELINE(); return yD_ONEHOT0;}
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/* Keywords */
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"always_comb" {yylval.fileline = CRELINE(); return yALWAYS;}
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"always_ff" {yylval.fileline = CRELINE(); return yALWAYS;}
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"always_latch" {yylval.fileline = CRELINE(); return yALWAYS;}
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"final" {yylval.fileline = CRELINE(); return yFINAL;}
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/* Generic unsupported warnings */
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/* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */
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"alias" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
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"bind" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
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@ -425,8 +393,9 @@ escid \\[^ \t\f\r\n]+
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"with" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
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}
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/* SystemVerilog ONLY not PSL; different rules for PSL as specified below */
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<S05>{
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/* Verilog ONLY not PSL; different rules for PSL as specified below */
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/* Generic unsupported warnings */
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"assert" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);}
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"assume" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);}
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"before" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);}
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@ -438,8 +407,36 @@ escid \\[^ \t\f\r\n]+
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"within" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);}
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}
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/* Default PLI rule */
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<V95,V01,V05,S05,PSL>{
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"$"[a-zA-Z_$]+ {yyerrorf("Unsupported or unknown PLI call: %s",yytext);}
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}
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/************************************************************************/
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/* PSL */
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/*Entry into PSL; mode change */
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<V95,V01,V05,S05>{
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"psl" { yy_push_state(PSL); yylval.fileline = CRELINE(); return yPSL; }
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}
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<PSL>{
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/* PSL reserved */
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/* Special things */
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"psl" { ; } // 'psl' may occur in middle of statement, so easier just to suppress
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/* Keywords */
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"assert" {yylval.fileline = CRELINE(); return yASSERT;}
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"assume" {yylval.fileline = CRELINE(); return yASSERT;} //==assert
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"before_!" {yyerrorf("Illegal syntax, use before!_ instead of %s",yytext);}
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"clock" {yylval.fileline = CRELINE(); return yCLOCK;}
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"countones" {yylval.fileline = CRELINE(); return yD_COUNTONES;}
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"cover" {yylval.fileline = CRELINE(); return yCOVER;}
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"isunknown" {yylval.fileline = CRELINE(); return yD_ISUNKNOWN;}
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"onehot" {yylval.fileline = CRELINE(); return yD_ONEHOT; }
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"onehot0" {yylval.fileline = CRELINE(); return yD_ONEHOT0; }
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"until_!" {yyerrorf("Illegal syntax, use until!_ instead of %s",yytext);}
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"report" {yylval.fileline = CRELINE(); return yREPORT; }
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"true" {yylval.fileline = CRELINE(); return yTRUE; }
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/* Generic unsupported warnings */
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/*"A" {yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
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/*"AF" {yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
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/*"AG" {yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */
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@ -504,6 +501,9 @@ escid \\[^ \t\f\r\n]+
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"within" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);}
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}
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/************************************************************************/
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/* Meta comments */
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/* Converted from //{cmt}verilator ...{cmt} by preprocessor */
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<V95,V01,V05,S05,PSL>{
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"/*verilator clock_enable*/" {yylval.fileline = CRELINE(); return yVL_CLOCK_ENABLE;}
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@ -527,6 +527,9 @@ escid \\[^ \t\f\r\n]+
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"/*"[^*]*"*/" {V3Read::verilatorCmtBad(yytext); }
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}
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/************************************************************************/
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/* Operators */
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/* Verilog 1995 Operators */
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<V95,V01,V05,S05,PSL>{
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"&&" {yylval.fileline = CRELINE(); return yANDAND;}
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