diff --git a/Changes b/Changes index a9d57a947..6f93bcbaf 100644 --- a/Changes +++ b/Changes @@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks! *** Support $fseek, $ftell, $frewind, bug1496. [Howard Su] +*** Add --public-flat-rw, bug1511. [Stefan Wallentowitz] + **** Fix make test with no VERILATOR_ROOT, bug1494. [Ahmed El-Mahmoudy] **** Make Syms file honor --output-split-cfuncs, bug1499. [Todd Strader] diff --git a/bin/verilator b/bin/verilator index 9c50a6338..dbea9ab03 100755 --- a/bin/verilator +++ b/bin/verilator @@ -354,6 +354,7 @@ detailed descriptions in L for more information. --prof-threads Enable generating gantt chart data for threads --private Debugging; see docs --public Debugging; see docs + --public-flat-rw Mark all variables, etc as public_flat_rw -pvalue+= Overwrite toplevel parameter --quiet-exit Don't print the command on failure --relative-includes Resolve includes relative to current file @@ -1168,6 +1169,16 @@ inlining. This will also turn off inlining as if all modules had a /*verilator public_module*/, unless the module specifically enabled it with /*verilator inline_module*/. +=item --public-flat-rw + +Declares all variables, ports and wires public as if they had /*verilator +public_flat_rw*/ comments. This will make them VPI accessible by their +flat name, but not turn off module inlining. This is particularly useful +in combination with --vpi. This may also in some rare cases result in +mis-simulation of generated clocks. Instead of this global switch, marking +only those signals that need public_flat_rw is typically significantly +better performing. + =item -pvalue+I=I Overwrites the given parameter(s) of the toplevel module. See -G for a @@ -2916,7 +2927,8 @@ signal should be declared public_flat (see above), but read-only. Used after an input, output, register, or wire declaration to indicate the signal should be declared public_flat_rd (see above), and also writable, where writes should be considered to have the timing specified by the given -sensitivity edge list. +sensitivity edge list. Set for all variables, ports and wires using the +--public-flat-rw switch. =item /*verilator public_module*/ diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 38e17c2a0..95c7d52a7 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -10,6 +10,7 @@ Howard Su Jeremy Bennett John Coiner Kanad Kanhere +Lukasz Dalek Maarten De Braekeleer Philipp Wagner Richard Myers diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index 75d8d71d0..021535242 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -189,6 +189,17 @@ private: return; } + if (v3Global.opt.publicFlatRW()) { + switch (nodep->varType()) { + case AstVarType::VAR: + case AstVarType::PORT: + case AstVarType::WIRE: + nodep->sigUserRWPublic(true); + break; + default: break; + } + } + // We used modTrace before leveling, and we may now // want to turn it off now that we know the levelizations if (v3Global.opt.traceDepth() @@ -198,6 +209,7 @@ private: nodep->trace(false); } m_varp = nodep; + iterateChildren(nodep); m_varp = NULL; // temporaries under an always aren't expected to be blocking diff --git a/src/V3Options.cpp b/src/V3Options.cpp index a219f9e05..14cd82afb 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -696,6 +696,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char else if ( onoff (sw, "-profile-cfuncs", flag/*ref*/)) { m_profCFuncs = flag; } // Undocumented, for backward compat else if ( onoff (sw, "-prof-threads", flag/*ref*/)) { m_profThreads = flag; } else if ( onoff (sw, "-public", flag/*ref*/)) { m_public = flag; } + else if ( onoff (sw, "-public-flat-rw", flag/*ref*/) ) { m_publicFlatRW = flag; v3Global.dpi(true); } else if (!strncmp(sw, "-pvalue+", strlen("-pvalue+"))) { addParameter(string(sw+strlen("-pvalue+")), false); } else if ( onoff (sw, "-relative-cfuncs", flag/*ref*/)) { m_relativeCFuncs = flag; } else if ( onoff (sw, "-relative-includes", flag/*ref*/)) { m_relativeIncludes = flag; } @@ -1297,6 +1298,7 @@ V3Options::V3Options() { m_preprocOnly = false; m_preprocNoLine = false; m_public = false; + m_publicFlatRW = false; m_relativeCFuncs = true; m_relativeIncludes = false; m_reportUnoptflat = false; diff --git a/src/V3Options.h b/src/V3Options.h index 01c4b9bad..c4e6e9735 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -135,6 +135,7 @@ class V3Options { bool m_profCFuncs; // main switch: --prof-cfuncs bool m_profThreads; // main switch: --prof-threads bool m_public; // main switch: --public + bool m_publicFlatRW; // main switch: --public-flat-rw bool m_relativeCFuncs; // main switch: --relative-cfuncs bool m_relativeIncludes; // main switch: --relative-includes bool m_reportUnoptflat; // main switch: --report-unoptflat @@ -309,6 +310,7 @@ class V3Options { bool profCFuncs() const { return m_profCFuncs; } bool profThreads() const { return m_profThreads; } bool allPublic() const { return m_public; } + bool publicFlatRW() const { return m_publicFlatRW; } bool lintOnly() const { return m_lintOnly; } bool ignc() const { return m_ignc; } bool inhibitSim() const { return m_inhibitSim; } diff --git a/test_regress/t/t_vpi_get.cpp b/test_regress/t/t_vpi_get.cpp index 3b51a5b91..e49a0f946 100644 --- a/test_regress/t/t_vpi_get.cpp +++ b/test_regress/t/t_vpi_get.cpp @@ -246,7 +246,7 @@ int main(int argc, char **argv, char **env) { Verilated::commandArgs(argc, argv); Verilated::debug(0); - VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out + Vt_vpi_get* topp = new Vt_vpi_get(""); // Note null name - we're flattening it out #ifdef VERILATOR # ifdef TEST_VERBOSE diff --git a/test_regress/t/t_vpi_get.pl b/test_regress/t/t_vpi_get.pl index 893ef732c..6e0ee3bae 100755 --- a/test_regress/t/t_vpi_get.pl +++ b/test_regress/t/t_vpi_get.pl @@ -18,7 +18,7 @@ compile( verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_get.cpp"], make_pli => 1, iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], - v_flags2 => ["+define+USE_VPI_NOT_DPI"], + v_flags2 => ["+define+USE_VPI_NOT_DPI +define+VERILATOR_COMMENTS"], ); execute( diff --git a/test_regress/t/t_vpi_get.v b/test_regress/t/t_vpi_get.v index 4bc474050..ca4709391 100644 --- a/test_regress/t/t_vpi_get.v +++ b/test_regress/t/t_vpi_get.v @@ -11,13 +11,21 @@ import "DPI-C" context function integer mon_check(); `endif +`ifdef VERILATOR_COMMENTS + `define PUBLIC_FLAT_RD /*verilator public_flat_rd*/ + `define PUBLIC_FLAT_RW /*verilator public_flat_rw @(posedge clk)*/ +`else + `define PUBLIC_FLAT_RD + `define PUBLIC_FLAT_RW +`endif + module t (/*AUTOARG*/ // Inputs - input clk /*verilator public_flat_rd */, + input clk `PUBLIC_FLAT_RD, // test ports - input [15:0] testin /*verilator public_flat_rd */, - output [23:0] testout /*verilator public_flat_rw @(posedge clk) */ + input [15:0] testin `PUBLIC_FLAT_RD, + output [23:0] testout `PUBLIC_FLAT_RW ); @@ -27,10 +35,10 @@ extern "C" int mon_check(); `verilog `endif - reg onebit /*verilator public_flat_rw @(posedge clk) */; - reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */; - reg onetwo [1:2] /*verilator public_flat_rw @(posedge clk) */; - reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; + reg onebit `PUBLIC_FLAT_RW; + reg [2:1] twoone `PUBLIC_FLAT_RW; + reg onetwo [1:2] `PUBLIC_FLAT_RW; + reg [2:1] fourthreetwoone[4:3] `PUBLIC_FLAT_RW; integer status; @@ -39,8 +47,8 @@ extern "C" int mon_check(); wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3]; `endif - wire subin /*verilator public_flat_rd*/; - wire subout /*verilator public_flat_rd*/; + wire subin `PUBLIC_FLAT_RD; + wire subout `PUBLIC_FLAT_RD; sub sub(.*); // Test loop @@ -65,7 +73,7 @@ extern "C" int mon_check(); endmodule : t module sub ( - input subin /*verilator public_flat_rd*/, - output subout /*verilator public_flat_rd*/ + input subin `PUBLIC_FLAT_RD, + output subout `PUBLIC_FLAT_RD ); endmodule : sub diff --git a/test_regress/t/t_vpi_get_public_rw_switch.pl b/test_regress/t/t_vpi_get_public_rw_switch.pl new file mode 100755 index 000000000..ad0c83f9a --- /dev/null +++ b/test_regress/t/t_vpi_get_public_rw_switch.pl @@ -0,0 +1,36 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2010 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(simulator => 1); + +skip("Known compiler limitation") + if $Self->cxx_version =~ /\(GCC\) 4.4/; + +VM_PREFIX("Vt_vpi_get"); +top_filename("t/t_vpi_get.v"); +pli_filename("t_vpi_get.cpp"); + +compile( + make_top_shell => 0, + make_main => 0, + verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb' --exe --vpi" + ." --public-flat-rw --prefix Vt_vpi_get --no-l2name" + ." $Self->{t_dir}/t_vpi_get.cpp"], + make_pli => 1, + iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI"], + v_flags2 => ["+define+USE_VPI_NOT_DPI"], +); + +execute( + iv_pli => 1, + check_finished => 1 +); + +ok(1); +1;