diff --git a/Changes b/Changes
index ab8671590..2b7082619 100644
--- a/Changes
+++ b/Changes
@@ -50,6 +50,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix duplicate implicit variables under generates, bug201. [Byron Bradley]
 
+**** Fix for variable typing, bug205.  [by Byron Bradley]
+
 **** Fix tracing with --pins-bv 1, bug195.  [Michael S]
 
 **** Fix MinGW compilation, bug184. [by Shankar Giri]
diff --git a/src/verilog.y b/src/verilog.y
index 86d78fecd..faad7dfbb 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1945,10 +1945,10 @@ caseCondList<nodep>:		// IEEE: part of case_item
 // "datatype id = x {, id = x }"  |  "yaId = x {, id=x}" is legal
 for_initialization<nodep>:	// ==IEEE: for_initialization + for_variable_declaration + extra terminating ";"
 	//			// IEEE: for_variable_declaration
-		data_type idAny/*new*/ '=' expr ';'
-			{ VARDTYPE($1);
-			  $$ = VARDONEA(*$2,NULL,NULL);
-			  $$->addNext(new AstAssign($3,new AstVarRef($3,*$2,true),$4));}
+		varRESET data_type idAny/*new*/ '=' expr ';'
+			{ VARDTYPE($2);
+			  $$ = VARDONEA(*$3,NULL,NULL);
+			  $$->addNext(new AstAssign($4,new AstVarRef($4,*$3,true),$5));}
 	|	varRefBase '=' expr ';'			{ $$ = new AstAssign($2,$1,$3); }
 	//UNSUP: List of initializations
 	;