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Support chandle

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This commit is contained in:
Wilson Snyder 2009-11-24 09:11:25 -05:00
parent c7d8eb126f
commit d2a27a84cf
6 changed files with 24 additions and 11 deletions
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8
Changes
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@ -5,8 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.7**
** Support byte, shortint, int, longint, time, var and void in variables,
parameters and functions.
** Support SystemVerilog types "byte", "chandle", "int", "longint",
"shortint", "time", "var" and "void" in variables and functions.
** Support "program", "package", "import" and $unit.
@ -22,12 +22,12 @@ indicates the contributor was also the author of the fix; Thanks!
*** Add VARHIDDEN warning when signal name hides module name.
**** Fix MinGW compilation, bug184. [by Shankar Giri]
**** Support optional cell parenthesis, bug179. [by Byron Bradley]
**** Support for loop i++, ++i, i--, --i, bug175. [by Byron Bradley]
**** Fix MinGW compilation, bug184. [by Shankar Giri]
**** Fix `define argument mis-replacing system task of same name, bug191.
**** Fix Verilator core dump on wide integer divides, bug178. [Byron Bradley]

5
bin/verilator
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@ -1706,6 +1706,11 @@ supply1, task, time, tri, typedef, var, vectored, while, wire, xnor, xor
Generally supported.
=item chandle
Treated as a "longint"; does not yet warn about operations that are
specified as illegal on chandles.
=item priority if, unique if
Priority and unique if's are treated as normal ifs and not asserted to be

11
src/V3Ast.h
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@ -204,16 +204,16 @@ public:
class AstBasicDTypeKwd {
public:
enum en {
BYTE, SHORTINT, INT, LONGINT, INTEGER, TIME, BIT,
LOGIC, SHORTREAL, REAL, REALTIME,
BIT, BYTE, CHANDLE, INT, INTEGER, LOGIC, LONGINT,
REAL, REALTIME, SHORTINT, SHORTREAL, TIME,
// Internal types
LOGIC_IMPLICIT
};
enum en m_e;
const char* ascii() const {
static const char* names[] = {
"byte", "shortint", "int", "longint", "integer", "time", "bit",
"logic", "shortreal", "real", "realtime",
"bit", "byte", "chandle", "int", "integer", "logic", "longint",
"real", "realtime", "shortint", "shortreal", "time",
"LOGIC_IMPLICIT"
};
return names[m_e];
@ -226,6 +226,7 @@ public:
switch (m_e) {
case BIT: return 1;
case BYTE: return 8;
case CHANDLE: return 64;
case INT: return 32;
case INTEGER: return 32;
case LOGIC: return 1;
@ -242,7 +243,7 @@ public:
return m_e==INTEGER || m_e==LOGIC || m_e==LOGIC_IMPLICIT;
}
int isZeroInit() const { // Otherwise initializes to X
return m_e==BIT || m_e==BYTE || m_e==INT || m_e==LONGINT || m_e==SHORTINT;
return m_e==BIT || m_e==BYTE || m_e==CHANDLE || m_e==INT || m_e==LONGINT || m_e==SHORTINT;
}
int isSloppy() const { // Don't be as anal about width warnings
return !(m_e==LOGIC || m_e==BIT);

2
src/verilog.l
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@ -367,6 +367,7 @@ escid \\[^ \t\f\r\n]+
"always_latch" { FL; return yALWAYS; }
"bit" { FL; return yBIT; }
"byte" { FL; return yBYTE; }
"chandle" { FL; return yCHANDLE; }
"clocking" { FL; return yCLOCKING; }
"do" { FL; return yDO; }
"endclocking" { FL; return yENDCLOCKING; }
@ -398,7 +399,6 @@ escid \\[^ \t\f\r\n]+
"bins" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"binsof" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"break" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"chandle" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"class" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"constraint" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"context" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }

3
src/verilog.y
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@ -248,6 +248,7 @@ class AstSenTree;
%token<fl> yCASE "case"
%token<fl> yCASEX "casex"
%token<fl> yCASEZ "casez"
%token<fl> yCHANDLE "chandle"
%token<fl> yCLOCKING "clocking"
%token<fl> yCOVER "cover"
%token<fl> yDEFAULT "default"
@ -1047,7 +1048,7 @@ data_typeNoRef<dtypep>: // ==IEEE: data_type, excluding class_type etc referenc
//UNSUP { UNSUP }
//UNSUP enumDecl { UNSUP }
//UNSUP ySTRING { UNSUP }
//UNSUP yCHANDLE { UNSUP }
| yCHANDLE { $$ = new AstBasicDType($1,AstBasicDTypeKwd::CHANDLE); }
//UNSUP yEVENT { UNSUP }
//UNSUP yVIRTUAL__INTERFACE yINTERFACE id/*interface*/ { UNSUP }
//UNSUP yVIRTUAL__anyID id/*interface*/ { UNSUP }

6
test_regress/t/t_var_types.v
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@ -12,6 +12,7 @@ module t (/*AUTOARG*/);
longint d_longint;
integer d_integer;
time d_time;
chandle d_chandle;
// IEEE: integer_atom_type
bit d_bit;
@ -64,6 +65,7 @@ module t (/*AUTOARG*/);
function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction
function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction
function time f_time; time lv_time; f_time = lv_time; endfunction
function chandle f_chandle; chandle lv_chandle; f_chandle = lv_chandle; endfunction
// verilator lint_on WIDTH
`ifdef verilator
@ -104,6 +106,9 @@ module t (/*AUTOARG*/);
// verilator lint_on WIDTH
// verilator lint_on UNSIGNED
// Can't CHECK_ALL(d_chandle), as many operations not legal on chandles
if ($bits(d_chandle) !== 64) $stop;
`define CHECK_P(name,nbits) \
if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \
@ -134,6 +139,7 @@ module t (/*AUTOARG*/);
`CHECK_F(f_longint ,64,1'b1);
`CHECK_F(f_integer ,32,1'b0);
`CHECK_F(f_time ,64,1'b0);
`CHECK_F(f_chandle ,64,1'b0);
`CHECK_F(f_bit ,1 ,1'b1);
`CHECK_F(f_logic ,1 ,1'b0);
`CHECK_F(f_reg ,1 ,1'b0);