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Fix mis-extending red xor/xand operators.

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Wilson Snyder 2014-04-09 07:58:46 -04:00
parent fb4928b2f5
commit d04eb977c2
3 changed files with 11 additions and 3 deletions
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2
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@ -25,7 +25,7 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix modport function import not-found error.
**** Fix signed extension problems with -Wno-WIDTH, bug729. [Clifford Wolf]
**** Fix expression width problems with -Wno-WIDTH, bug729, bug736. [Clifford Wolf]
**** Fix power operator calculation, bug730, bug735. [Clifford Wolf]

4
src/verilog.y
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@ -2845,8 +2845,8 @@ expr<nodep>: // IEEE: part of expression/constant_expression/primary
| '~' ~r~expr %prec prNEGATION { $$ = new AstNot ($1,$2); }
| '|' ~r~expr %prec prREDUCTION { $$ = new AstRedOr ($1,$2); }
| '^' ~r~expr %prec prREDUCTION { $$ = new AstRedXor ($1,$2); }
| yP_NAND ~r~expr %prec prREDUCTION { $$ = new AstNot($1,new AstRedAnd($1,$2)); }
| yP_NOR ~r~expr %prec prREDUCTION { $$ = new AstNot($1,new AstRedOr ($1,$2)); }
| yP_NAND ~r~expr %prec prREDUCTION { $$ = new AstLogNot($1,new AstRedAnd($1,$2)); }
| yP_NOR ~r~expr %prec prREDUCTION { $$ = new AstLogNot($1,new AstRedOr ($1,$2)); }
| yP_XNOR ~r~expr %prec prREDUCTION { $$ = new AstRedXnor ($1,$2); }
//
// // IEEE: inc_or_dec_expression

8
test_regress/t/t_math_arith.v
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@ -111,6 +111,14 @@ module t (/*AUTOARG*/
// Test display extraction widthing
$display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]);
// bug736
//verilator lint_off WIDTH
if ((~| 4'b0000) != 4'b0001) $stop;
if ((~| 4'b0010) != 4'b0000) $stop;
if ((~& 4'b1111) != 4'b0000) $stop;
if ((~& 4'b1101) != 4'b0001) $stop;
//verilator lint_on WIDTH
$write("*-* All Finished *-*\n");
$finish;
end