From cf7f49e1398aed74e9d63b0c3ab5093c6bcf744d Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 13 Apr 2021 09:25:11 -0400 Subject: [PATCH] Docs: Fix cross-references --- README.rst | 27 +++++++++------------------ bin/verilator | 8 ++++---- bin/verilator_coverage | 6 ++++-- bin/verilator_gantt | 6 ++++-- bin/verilator_profcfunc | 6 ++++-- 5 files changed, 25 insertions(+), 28 deletions(-) diff --git a/README.rst b/README.rst index 8591c7587..d13cd58ba 100644 --- a/README.rst +++ b/README.rst @@ -23,15 +23,15 @@ Welcome to Verilator * Compiles into multithreaded C++, or SystemC * Creates XML to front-end your own tools - |Logo| - * - |verilator multithreaded performance bg min| + * - |verilator multithreaded performance| - **Fast** * Outperforms many commercial simulators * Single- and multi-threaded output models * - **Widely Used** * Wide industry and academic deployment * Out-of-the-box support from Arm, and RISC-V vendor IP - - |verilator usage 400x200 min| - * - |verilator community 400x125 min| + - |verilator usage| + * - |verilator community| - **Community Driven & Openly Licensed** * Guided by the `CHIPS Alliance`_ and `Linux Foundation`_ * Open, and free as in both speech and beer @@ -40,7 +40,7 @@ Welcome to Verilator * Commercial support contracts * Design support contracts * Enhancement contracts - - |verilator support 400x125 min| + - |verilator support| What Verilator Does @@ -85,15 +85,6 @@ Modelsim, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on computes rather than licenses. Thus Verilator gives you the best cycles/dollar. -For more information on how Verilator stacks up to some of the other -closed-sourced and open-sourced Verilog simulators, see the `Verilog -Simulator Benchmarks -`_. (If you -benchmark Verilator, please see the notes in the `Verilator manual (PDF) -`_, and also if possible post on -the forums the results; there may be additional tweaks possible.) - - Installation & Documentation ============================ @@ -123,7 +114,7 @@ We appreciate and welcome your contributions in whatever form; please see `Contributing to Verilator `_. Thanks to our `Contributors and Sponsors -`_. +`_. Verilator also supports and encourages commercial support models and organizations; please see `Verilator Commercial Support @@ -154,7 +145,7 @@ Perl Artistic License Version 2.0. See the documentation for more details. .. _Icarus Verilog: http://iverilog.icarus.com .. _Linux Foundation: https://www.linuxfoundation.org .. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png -.. |verilator multithreaded performance bg min| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png -.. |verilator usage 400x200 min| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png -.. |verilator community 400x125 min| image:: https://www.veripool.org/img/verilator_community_400x125-min.png -.. |verilator support 400x125 min| image:: https://www.veripool.org/img/verilator_support_400x125-min.png +.. |verilator multithreaded performance| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png +.. |verilator usage| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png +.. |verilator community| image:: https://www.veripool.org/img/verilator_community_400x125-min.png +.. |verilator support| image:: https://www.veripool.org/img/verilator_support_400x125-min.png diff --git a/bin/verilator b/bin/verilator index 59fb5e608..9e1ce7094 100755 --- a/bin/verilator +++ b/bin/verilator @@ -263,8 +263,8 @@ For documentation see L. =head1 ARGUMENT SUMMARY This is a short summary of the arguments to the "verilator" executable. -See L for the detailed -descriptions of these arguments. +See L for the +detailed descriptions of these arguments. =for VL_SPHINX_EXTRACT "_build/gen/args_verilator.rst" @@ -432,8 +432,8 @@ descriptions of these arguments. This is a short summary of the simulation runtime arguments, i.e. for the final Verilated simulation runtime models. See -L for the detailed description of -these arguments. +L for the detailed +description of these arguments. =for VL_SPHINX_EXTRACT "_build/gen/args_verilated.rst" diff --git a/bin/verilator_coverage b/bin/verilator_coverage index e6ecbb77a..ab76d15ba 100755 --- a/bin/verilator_coverage +++ b/bin/verilator_coverage @@ -160,7 +160,8 @@ verilator_coverage - Verilator coverage analyzer Verilator_coverage processes Verilated model-generated coverage reports. -For documentation see L. +For documentation see +L. =head1 ARGUMENT SUMMARY @@ -199,7 +200,8 @@ C, C L which is the source for this document. -and L for detailed documentation. +and L for +detailed documentation. =cut diff --git a/bin/verilator_gantt b/bin/verilator_gantt index 2251d9f6a..8d043670d 100755 --- a/bin/verilator_gantt +++ b/bin/verilator_gantt @@ -539,7 +539,8 @@ Verilator_gantt creates a visual representation to help analyze Verilator multithreaded simulation performance, by showing when each macro-task starts and ends, and showing when each thread is busy or idle. -For documentation see L. +For documentation see +L. =head1 ARGUMENT SUMMARY @@ -564,7 +565,8 @@ SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 C -and L for detailed documentation. +and L for +detailed documentation. =cut diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc index 8dade5ef3..e0c5340bf 100755 --- a/bin/verilator_profcfunc +++ b/bin/verilator_profcfunc @@ -214,7 +214,8 @@ the functions are then transformed, assuming the user used Verilator's --prof-cfuncs, and a report printed showing the percentage of time, etc, in each Verilog block. -For documentation see L. +For documentation see +L. =head1 ARGUMENT SUMMARY @@ -236,7 +237,8 @@ SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 C -and L for detailed documentation. +and L for +detailed documentation. =cut