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Fix some errors reporting wrong objects.

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This commit is contained in:
Wilson Snyder 2019-07-14 12:09:40 -04:00
parent 173efbc829
commit cbb9288cb1
12 changed files with 36 additions and 26 deletions
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16
src/V3Active.cpp
View File

@ -168,13 +168,14 @@ private:
// Convert to a non-delayed assignment
UINFO(5," ASSIGNDLY "<<nodep<<endl);
if (m_check == CT_INITIAL) {
nodep->v3warn(INITIALDLY, "Delayed assignments (<=) in initial"
" or final block; suggest blocking assignments (=).");
nodep->v3warn(INITIALDLY, "Delayed assignments (<=) in initial or final block\n"
<<nodep->warnMore()<<"... Suggest blocking assignments (=)");
} else if (m_check == CT_LATCH) {
// Suppress. Shouldn't matter that the interior of the latch races
} else {
nodep->v3warn(COMBDLY, "Delayed assignments (<=) in non-clocked"
" (non flop or latch) block; suggest blocking assignments (=).");
" (non flop or latch) block\n"
<<nodep->warnMore()<<"... Suggest blocking assignments (=)");
}
AstNode* newp = new AstAssign(nodep->fileline(),
nodep->lhsp()->unlinkFrBack(),
@ -196,16 +197,15 @@ private:
if (m_check == CT_SEQ
&& m_assignp
&& !varp->isUsedLoopIdx() // Ignore loop indicies
&& !varp->isTemp()
) {
&& !varp->isTemp()) {
// Allow turning off warnings on the always, or the variable also
if (!m_alwaysp->fileline()->warnIsOff(V3ErrorCode::BLKSEQ)
&& !m_assignp->fileline()->warnIsOff(V3ErrorCode::BLKSEQ)
&& !varp->fileline()->warnIsOff(V3ErrorCode::BLKSEQ)
) {
&& !varp->fileline()->warnIsOff(V3ErrorCode::BLKSEQ)) {
m_assignp->v3warn(BLKSEQ, "Blocking assignments (=) in sequential (flop or latch) block\n"
<<m_assignp->warnMore()<<"... Suggest delayed assignments (<=)");
m_alwaysp->fileline()->modifyWarnOff(V3ErrorCode::BLKSEQ, true); // Complain just once for the entire always
varp->fileline()->modifyWarnOff(V3ErrorCode::BLKSEQ, true);
nodep->v3warn(BLKSEQ, "Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).");
}
}
}

6
src/V3Case.cpp
View File

@ -72,7 +72,7 @@ private:
itemp; itemp=VN_CAST(itemp->nextp(), CaseItem)) {
if (itemp->isDefault()) {
if (hitDefault) {
nodep->v3error("Multiple default statements in case statement.");
itemp->v3error("Multiple default statements in case statement.");
}
hitDefault = true;
}
@ -186,8 +186,8 @@ private:
if (!m_valueItem[i]) {
m_valueItem[i] = itemp;
} else if (!itemp->ignoreOverlap() && !bitched) {
itemp->v3warn(CASEOVERLAP, "Case values overlap (example pattern 0x"
<<std::hex<<i<<")");
icondp->v3warn(CASEOVERLAP, "Case values overlap (example pattern 0x"
<<std::hex<<i<<")");
bitched = true;
m_caseNoOverlapsAllCovered = false;
}

2
src/V3Delayed.cpp
View File

@ -166,7 +166,7 @@ private:
MULTIDRIVEN, "Signal has multiple driving blocks with different clocking: "
<<varrefp->varp()->prettyNameQ()<<endl
<<varrefp->warnOther()<<"... Location of first driving block"<<endl
<<varrefp->varp()->warnContextPrimary()<<endl
<<varrefp->warnContextPrimary()<<endl
<<oldactivep->warnOther()<<"... Location of other driving block"<<endl
<<oldactivep->warnContextSecondary()
);

6
src/V3Inst.cpp
View File

@ -337,8 +337,10 @@ private:
// Arrayed instants: one bit for each of the instants (each
// assign is 1 pinwidth wide)
if (m_cellRangep->littleEndian()) {
nodep->v3warn(LITENDIAN, "Little endian cell range connecting to vector: MSB < LSB of cell range: "
<<m_cellRangep->lsbConst()<<":"<<m_cellRangep->msbConst());
nodep->exprp()->v3warn(
LITENDIAN,
"Little endian cell range connecting to vector: MSB < LSB of cell range: "
<<m_cellRangep->lsbConst()<<":"<<m_cellRangep->msbConst());
}
AstNode* exprp = nodep->exprp()->unlinkFrBack();
bool inputPin = nodep->modVarp()->isNonOutput();

9
src/V3Width.cpp
View File

@ -829,12 +829,15 @@ private:
V3Const::constifyParamsEdit(nodep->ticksp()); // ticksp may change
const AstConst* constp = VN_CAST(nodep->ticksp(), Const);
if (!constp || constp->toSInt() < 1) {
nodep->v3error("$past tick value must be constant and >= 1 (IEEE 2017 16.9.3)");
nodep->v3error("$past tick value must be constant (IEEE 2017 16.9.3)");
nodep->ticksp()->unlinkFrBack()->deleteTree();
} else if (constp->toSInt() < 1) {
constp->v3error("$past tick value must be >= 1 (IEEE 2017 16.9.3)");
nodep->ticksp()->unlinkFrBack()->deleteTree();
} else {
if (constp->toSInt() > 10) {
nodep->v3warn(TICKCOUNT, "$past tick value of "<<constp->toSInt()
<<" may have a large performance cost");
constp->v3warn(TICKCOUNT, "$past tick value of "<<constp->toSInt()
<<" may have a large performance cost");
}
}
}

2
test_regress/t/t_case_default_bad.out
View File

@ -1,2 +1,2 @@
%Error: t/t_case_default_bad.v:12: Multiple default statements in case statement.
%Error: t/t_case_default_bad.v:15: Multiple default statements in case statement.
%Error: Exiting due to

6
test_regress/t/t_initial_dlyass_bad.out
View File

@ -1,4 +1,6 @@
%Warning-INITIALDLY: t/t_initial_dlyass.v:17: Delayed assignments (<=) in initial or final block; suggest blocking assignments (=).
%Warning-INITIALDLY: t/t_initial_dlyass.v:17: Delayed assignments (<=) in initial or final block
: ... Suggest blocking assignments (=)
... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message.
%Warning-INITIALDLY: t/t_initial_dlyass.v:18: Delayed assignments (<=) in initial or final block; suggest blocking assignments (=).
%Warning-INITIALDLY: t/t_initial_dlyass.v:18: Delayed assignments (<=) in initial or final block
: ... Suggest blocking assignments (=)
%Error: Exiting due to

6
test_regress/t/t_lint_blksync_bad.out
View File

@ -1,6 +1,8 @@
%Warning-BLKSEQ: t/t_lint_blksync_bad.v:23: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).
%Warning-BLKSEQ: t/t_lint_blksync_bad.v:23: Blocking assignments (=) in sequential (flop or latch) block
: ... Suggest delayed assignments (<=)
... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message.
%Warning-COMBDLY: t/t_lint_blksync_bad.v:30: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).
%Warning-COMBDLY: t/t_lint_blksync_bad.v:30: Delayed assignments (<=) in non-clocked (non flop or latch) block
: ... Suggest blocking assignments (=)
*** See the manual before disabling this,
else you may end up with different sim results.
%Error: Exiting due to

2
test_regress/t/t_lint_blksync_bad.pl
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@ -7,7 +7,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(vlt_all => 1);
scenarios(linter => 1);
lint(
verilator_flags2 => ["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"],

3
test_regress/t/t_lint_latch_bad.out
View File

@ -1,4 +1,5 @@
%Warning-COMBDLY: t/t_lint_latch_bad.v:24: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).
%Warning-COMBDLY: t/t_lint_latch_bad.v:24: Delayed assignments (<=) in non-clocked (non flop or latch) block
: ... Suggest blocking assignments (=)
... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
*** See the manual before disabling this,
else you may end up with different sim results.

2
test_regress/t/t_past_bad.out
View File

@ -1,4 +1,4 @@
%Error: t/t_past_bad.v:11: $past tick value must be constant and >= 1 (IEEE 2017 16.9.3)
%Error: t/t_past_bad.v:11: $past tick value must be constant (IEEE 2017 16.9.3)
%Warning-TICKCOUNT: t/t_past_bad.v:12: $past tick value of 10000 may have a large performance cost
... Use "/* verilator lint_off TICKCOUNT */" and lint_on around source to disable this message.
%Error: Exiting due to

2
test_regress/t/t_past_bad.pl
View File

@ -7,7 +7,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(vlt_all => 1);
scenarios(vlt => 1);
compile(
fails => 1,