From cac50282eb9fdff20a27d58b52147f3ba627b326 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 26 Jan 2020 11:38:34 -0500
Subject: [PATCH] Fix pattern replication without key.

---
 src/V3Width.cpp                           |  5 +++--
 test_regress/t/t_array_pattern_unpacked.v | 24 ++++++++++++++++++-----
 2 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 83a3e306d..a37d5fec4 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -2300,9 +2300,10 @@ private:
                     patp->unlinkFrBack(&relinkHandle);
                     while (AstNode* movep = patp->lhssp()->nextp()) {
                         movep->unlinkFrBack();  // Not unlinkFrBackWithNext, just one
+                        AstNode* newkeyp = NULL;
+                        if (patp->keyp()) newkeyp = patp->keyp()->cloneTree(true);
                         AstPatMember* newp
-                            = new AstPatMember(patp->fileline(), movep,
-                                               patp->keyp()->cloneTree(true), NULL);
+                            = new AstPatMember(patp->fileline(), movep, newkeyp, NULL);
                         patp->addNext(newp);
                     }
                     relinkHandle.relink(patp);
diff --git a/test_regress/t/t_array_pattern_unpacked.v b/test_regress/t/t_array_pattern_unpacked.v
index 9aea2cb6a..903c8eaae 100644
--- a/test_regress/t/t_array_pattern_unpacked.v
+++ b/test_regress/t/t_array_pattern_unpacked.v
@@ -7,14 +7,18 @@ module t (/*AUTOARG*/);
 
    logic [3:0] array_simp [1:0] [3:0];  // big endian array
 
+   int         irep[1:2][1:6];
+
    initial begin
       array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
-      if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop;
+      if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
+          !== 16'h3210) $stop;
 
       // verilator lint_off WIDTH
       array_simp[0] = '{ 3 ,2 ,1, 0 };
       // verilator lint_on WIDTH
-      if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop;
+      if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
+          !== 16'h3210) $stop;
 
       // Doesn't seem to work for unpacked arrays in other simulators
       //array_simp[0] = '{ 1:4'd3, default:13 };
@@ -22,21 +26,31 @@ module t (/*AUTOARG*/);
 
       array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
       if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
-	   array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_1234) $stop;
+           array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
+          !== 32'h3210_1234) $stop;
 
       // Doesn't seem to work for unpacked arrays in other simulators
       array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
       if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
-	   array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_3210) $stop;
+           array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
+          !== 32'h3210_3210) $stop;
 
       array_simp = '{2{ '{4{ 4'd3 }} }};
       if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
-	   array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3333_3333) $stop;
+           array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
+          !== 32'h3333_3333) $stop;
 
       // Not legal in other simulators - replication doesn't match
       // However IEEE suggests this is legal.
       //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }};  // Note it's not '{3,2}
 
+      // Replication
+      irep = '{2{ '{3 {4, 5}}}};
+      if ({irep[1][1], irep[1][2], irep[1][3], irep[1][4], irep[1][5], irep[1][6]}
+          != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop;
+      if ({irep[2][1], irep[2][2], irep[2][3], irep[2][4], irep[2][5], irep[2][6]}
+          != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop;
+
       $write("*-* All Finished *-*\n");
       $finish;
    end